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ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU
During __v{6,7}_setup, we invalidate the TLBs since we are about to enable the MMU on return to head.S. Unfortunately, without a subsequent dsb instruction, the invalidation is not guaranteed to have completed by the time we write to the sctlr, potentially exposing us to junk/stale translations cached in the TLB. This patch reworks the init functions so that the dsb used to ensure completion of cache/predictor maintenance is also used to ensure completion of the TLB invalidation. Cc: <stable@vger.kernel.org> Reported-by: Albin Tonnerre <Albin.Tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -208,7 +208,6 @@ __v6_setup:
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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@ -218,6 +217,8 @@ __v6_setup:
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ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
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ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
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mcr p15, 0, r8, c2, c0, 1 @ load TTB1
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mcr p15, 0, r8, c2, c0, 1 @ load TTB1
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#endif /* CONFIG_MMU */
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#endif /* CONFIG_MMU */
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
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@ complete invalidations
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adr r5, v6_crval
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adr r5, v6_crval
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ldmia r5, {r5, r6}
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ldmia r5, {r5, r6}
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ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
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ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
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@ -351,7 +351,6 @@ __v7_setup:
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4: mov r10, #0
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4: mov r10, #0
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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dsb
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#ifdef CONFIG_MMU
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
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v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
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@ -360,6 +359,7 @@ __v7_setup:
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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#endif
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#endif
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dsb @ Complete invalidations
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#ifndef CONFIG_ARM_THUMBEE
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#ifndef CONFIG_ARM_THUMBEE
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mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
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mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
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and r0, r0, #(0xf << 12) @ ThumbEE enabled field
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and r0, r0, #(0xf << 12) @ ThumbEE enabled field
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