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irqchip: spear_shirq: Namespace cleanup
The struct members of the shirq block struct are named to confuse the hell out of the casual reader. Clean it up. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lkml.kernel.org/r/20140619212713.219411832@linutronix.de Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Gleixner
Jason Cooper
parent
f37ecbce8b
commit
c5d1d85748
@ -47,20 +47,20 @@ struct shirq_regs {
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/*
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* struct spear_shirq: shared irq structure
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*
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* irq_base: base irq in linux domain
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* irq_nr: no. of shared interrupts in a particular block
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* irq_bit_off: starting bit offset in the status register
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* invalid_irq: irq group is currently disabled
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* base: base address of shared irq register
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* regs: register configuration for shared irq block
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* base: Base register address
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* regs: Register configuration for shared irq block
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* virq_base: Base virtual interrupt number
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* nr_irqs: Number of interrupts handled by this block
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* offset: Bit offset of the first interrupt
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* disabled: Group is disabled, but accounted
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*/
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struct spear_shirq {
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u32 irq_base;
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u32 irq_nr;
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u32 irq_bit_off;
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int invalid_irq;
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void __iomem *base;
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struct shirq_regs regs;
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void __iomem *base;
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struct shirq_regs regs;
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u32 virq_base;
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u32 nr_irqs;
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u32 offset;
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bool disabled;
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};
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static DEFINE_SPINLOCK(lock);
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@ -70,8 +70,8 @@ static DEFINE_SPINLOCK(lock);
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#define SPEAR300_INT_STS_MASK_REG 0x58
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static struct spear_shirq spear300_shirq_ras1 = {
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.irq_nr = 9,
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.irq_bit_off = 0,
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.offset = 0,
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.nr_irqs = 9,
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.regs = {
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.enb_reg = SPEAR300_INT_ENB_MASK_REG,
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.status_reg = SPEAR300_INT_STS_MASK_REG,
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@ -87,8 +87,8 @@ static struct spear_shirq *spear300_shirq_blocks[] = {
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#define SPEAR310_INT_STS_MASK_REG 0x04
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static struct spear_shirq spear310_shirq_ras1 = {
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.irq_nr = 8,
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.irq_bit_off = 0,
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.offset = 0,
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.nr_irqs = 8,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -97,8 +97,8 @@ static struct spear_shirq spear310_shirq_ras1 = {
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};
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static struct spear_shirq spear310_shirq_ras2 = {
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.irq_nr = 5,
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.irq_bit_off = 8,
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.offset = 8,
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.nr_irqs = 5,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -107,8 +107,8 @@ static struct spear_shirq spear310_shirq_ras2 = {
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};
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static struct spear_shirq spear310_shirq_ras3 = {
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.irq_nr = 1,
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.irq_bit_off = 13,
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.offset = 13,
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.nr_irqs = 1,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -117,8 +117,8 @@ static struct spear_shirq spear310_shirq_ras3 = {
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};
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static struct spear_shirq spear310_shirq_intrcomm_ras = {
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.irq_nr = 3,
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.irq_bit_off = 14,
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.offset = 14,
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.nr_irqs = 3,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR310_INT_STS_MASK_REG,
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@ -139,8 +139,8 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
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#define SPEAR320_INT_ENB_MASK_REG 0x08
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static struct spear_shirq spear320_shirq_ras1 = {
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.irq_nr = 3,
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.irq_bit_off = 7,
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.offset = 7,
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.nr_irqs = 3,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -150,8 +150,8 @@ static struct spear_shirq spear320_shirq_ras1 = {
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};
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static struct spear_shirq spear320_shirq_ras2 = {
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.irq_nr = 1,
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.irq_bit_off = 10,
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.offset = 10,
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.nr_irqs = 1,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -161,9 +161,9 @@ static struct spear_shirq spear320_shirq_ras2 = {
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};
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static struct spear_shirq spear320_shirq_ras3 = {
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.irq_nr = 7,
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.irq_bit_off = 0,
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.invalid_irq = 1,
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.offset = 0,
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.nr_irqs = 7,
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.disabled = 1,
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.regs = {
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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.reset_to_enb = 1,
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@ -174,8 +174,8 @@ static struct spear_shirq spear320_shirq_ras3 = {
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};
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static struct spear_shirq spear320_shirq_intrcomm_ras = {
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.irq_nr = 11,
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.irq_bit_off = 11,
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.offset = 11,
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.nr_irqs = 11,
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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@ -194,7 +194,7 @@ static struct spear_shirq *spear320_shirq_blocks[] = {
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static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
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{
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struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
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u32 val, offset = d->irq - shirq->irq_base;
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u32 val, offset = d->irq - shirq->virq_base;
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unsigned long flags;
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if (shirq->regs.enb_reg == -1)
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@ -204,9 +204,9 @@ static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
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val = readl(shirq->base + shirq->regs.enb_reg);
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if (mask ^ shirq->regs.reset_to_enb)
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val &= ~(0x1 << shirq->irq_bit_off << offset);
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val &= ~(0x1 << shirq->offset << offset);
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else
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val |= 0x1 << shirq->irq_bit_off << offset;
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val |= 0x1 << shirq->offset << offset;
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writel(val, shirq->base + shirq->regs.enb_reg);
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spin_unlock_irqrestore(&lock, flags);
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@ -239,17 +239,17 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc)
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chip = irq_get_chip(irq);
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chip->irq_ack(&desc->irq_data);
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mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
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mask = ((0x1 << shirq->nr_irqs) - 1) << shirq->offset;
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while ((val = readl(shirq->base + shirq->regs.status_reg) &
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mask)) {
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val >>= shirq->irq_bit_off;
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for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
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val >>= shirq->offset;
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for (i = 0, j = 1; i < shirq->nr_irqs; i++, j <<= 1) {
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if (!(j & val))
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continue;
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generic_handle_irq(shirq->irq_base + i);
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generic_handle_irq(shirq->virq_base + i);
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/* clear interrupt */
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if (shirq->regs.clear_reg == -1)
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@ -257,9 +257,9 @@ static void shirq_handler(unsigned irq, struct irq_desc *desc)
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tmp = readl(shirq->base + shirq->regs.clear_reg);
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if (shirq->regs.reset_to_clear)
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tmp &= ~(j << shirq->irq_bit_off);
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tmp &= ~(j << shirq->offset);
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else
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tmp |= (j << shirq->irq_bit_off);
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tmp |= (j << shirq->offset);
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writel(tmp, shirq->base + shirq->regs.clear_reg);
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}
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}
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@ -271,24 +271,24 @@ static void __init spear_shirq_register(struct spear_shirq *shirq,
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{
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int i;
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if (shirq->invalid_irq)
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if (shirq->disabled)
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return;
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irq_set_chained_handler(parent_irq, shirq_handler);
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irq_set_handler_data(parent_irq, shirq);
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for (i = 0; i < shirq->irq_nr; i++) {
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irq_set_chip_and_handler(shirq->irq_base + i,
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for (i = 0; i < shirq->nr_irqs; i++) {
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irq_set_chip_and_handler(shirq->virq_base + i,
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&shirq_chip, handle_simple_irq);
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set_irq_flags(shirq->irq_base + i, IRQF_VALID);
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irq_set_chip_data(shirq->irq_base + i, shirq);
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set_irq_flags(shirq->virq_base + i, IRQF_VALID);
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irq_set_chip_data(shirq->virq_base + i, shirq);
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}
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}
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static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
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struct device_node *np)
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{
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int i, parent_irq, irq_base, hwirq = 0, irq_nr = 0;
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int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
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struct irq_domain *shirq_domain;
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void __iomem *base;
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@ -299,15 +299,15 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
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}
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for (i = 0; i < block_nr; i++)
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irq_nr += shirq_blocks[i]->irq_nr;
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nr_irqs += shirq_blocks[i]->nr_irqs;
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irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
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if (IS_ERR_VALUE(irq_base)) {
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virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (IS_ERR_VALUE(virq_base)) {
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pr_err("%s: irq desc alloc failed\n", __func__);
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goto err_unmap;
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}
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shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
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shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
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&irq_domain_simple_ops, NULL);
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if (WARN_ON(!shirq_domain)) {
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pr_warn("%s: irq domain init failed\n", __func__);
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@ -316,18 +316,18 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
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for (i = 0; i < block_nr; i++) {
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shirq_blocks[i]->base = base;
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shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
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shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
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hwirq);
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parent_irq = irq_of_parse_and_map(np, i);
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spear_shirq_register(shirq_blocks[i], parent_irq);
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hwirq += shirq_blocks[i]->irq_nr;
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hwirq += shirq_blocks[i]->nr_irqs;
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}
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return 0;
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err_free_desc:
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irq_free_descs(irq_base, irq_nr);
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irq_free_descs(virq_base, nr_irqs);
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err_unmap:
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iounmap(base);
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return -ENXIO;
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