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ARM: mmci: add dmaengine-based DMA support
Based on a patch from Linus Walleij. Add dmaengine based support for DMA to the MMCI driver, using the Primecell DMA engine interface. The changes over Linus' driver are: - rename txsize_threshold to dmasize_threshold, as this reflects the purpose more. - use 'mmci_dma_' as the function prefix rather than 'dma_mmci_'. - clean up requesting of dma channels. - don't release a single channel twice when it's shared between tx and rx. - get rid of 'dma_enable' bool - instead check whether the channel is NULL. - detect incomplete DMA at the end of a transfer. Some DMA controllers (eg, PL08x) are unable to be configured for scatter DMA and also listen to all four DMA request signals [BREQ,SREQ,LBREQ,LSREQ] from the MMCI. They can do one or other but not both. As MMCI uses LBREQ/LSREQ for the final burst/words, PL08x does not transfer the last few words. - map and unmap DMA buffers using the DMA engine struct device, not the MMCI struct device - the DMA engine is doing the DMA transfer, not us. - avoid double-unmapping of the DMA buffers on MMCI data errors. - don't check for negative values from the dmaengine tx submission function - Dan says this must never fail. - use new dmaengine helper functions rather than using the ugly function pointers directly. - allow DMA code to be fully optimized away using dma_inprogress() which is defined to constant 0 if DMA engine support is disabled. - request maximum segment size from the DMA engine struct device and set this appropriately. - removed checking of buffer alignment - the DMA engine should deal with its own restrictions on buffer alignment, not the individual DMA engine users. - removed setting DMAREQCTL - this confuses some DMA controllers as it causes LBREQ to be asserted for the last seven transfers, rather than six SREQ and one LSREQ. - removed burst setting - the DMA controller should not burst past the transfer size required to complete the DMA operation. Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
51d4375dd7
commit
c8ebae3703
@ -2,7 +2,7 @@
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* linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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* Copyright (C) 2010 ST-Ericsson AB.
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* Copyright (C) 2010 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -25,8 +25,10 @@
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/amba/mmci.h>
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#include <linux/regulator/consumer.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/amba/mmci.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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@ -186,6 +188,248 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
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sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
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}
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/*
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* All the DMA operation mode stuff goes inside this ifdef.
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* This assumes that you have a generic DMA device interface,
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* no custom DMA interfaces are supported.
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*/
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#ifdef CONFIG_DMA_ENGINE
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static void __devinit mmci_dma_setup(struct mmci_host *host)
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{
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struct mmci_platform_data *plat = host->plat;
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const char *rxname, *txname;
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dma_cap_mask_t mask;
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if (!plat || !plat->dma_filter) {
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dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
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return;
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}
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/* Try to acquire a generic DMA engine slave channel */
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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/*
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* If only an RX channel is specified, the driver will
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* attempt to use it bidirectionally, however if it is
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* is specified but cannot be located, DMA will be disabled.
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*/
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if (plat->dma_rx_param) {
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host->dma_rx_channel = dma_request_channel(mask,
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plat->dma_filter,
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plat->dma_rx_param);
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/* E.g if no DMA hardware is present */
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if (!host->dma_rx_channel)
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dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
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}
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if (plat->dma_tx_param) {
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host->dma_tx_channel = dma_request_channel(mask,
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plat->dma_filter,
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plat->dma_tx_param);
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if (!host->dma_tx_channel)
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dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
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} else {
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host->dma_tx_channel = host->dma_rx_channel;
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}
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if (host->dma_rx_channel)
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rxname = dma_chan_name(host->dma_rx_channel);
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else
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rxname = "none";
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if (host->dma_tx_channel)
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txname = dma_chan_name(host->dma_tx_channel);
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else
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txname = "none";
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dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
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rxname, txname);
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/*
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* Limit the maximum segment size in any SG entry according to
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* the parameters of the DMA engine device.
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*/
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if (host->dma_tx_channel) {
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struct device *dev = host->dma_tx_channel->device->dev;
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unsigned int max_seg_size = dma_get_max_seg_size(dev);
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if (max_seg_size < host->mmc->max_seg_size)
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host->mmc->max_seg_size = max_seg_size;
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}
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if (host->dma_rx_channel) {
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struct device *dev = host->dma_rx_channel->device->dev;
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unsigned int max_seg_size = dma_get_max_seg_size(dev);
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if (max_seg_size < host->mmc->max_seg_size)
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host->mmc->max_seg_size = max_seg_size;
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}
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}
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/*
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* This is used in __devinit or __devexit so inline it
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* so it can be discarded.
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*/
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static inline void mmci_dma_release(struct mmci_host *host)
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{
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struct mmci_platform_data *plat = host->plat;
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if (host->dma_rx_channel)
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dma_release_channel(host->dma_rx_channel);
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if (host->dma_tx_channel && plat->dma_tx_param)
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dma_release_channel(host->dma_tx_channel);
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host->dma_rx_channel = host->dma_tx_channel = NULL;
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}
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static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
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{
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struct dma_chan *chan = host->dma_current;
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enum dma_data_direction dir;
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u32 status;
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int i;
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/* Wait up to 1ms for the DMA to complete */
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for (i = 0; ; i++) {
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status = readl(host->base + MMCISTATUS);
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if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
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break;
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udelay(10);
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}
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/*
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* Check to see whether we still have some data left in the FIFO -
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* this catches DMA controllers which are unable to monitor the
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* DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
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* contiguous buffers. On TX, we'll get a FIFO underrun error.
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*/
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if (status & MCI_RXDATAAVLBLMASK) {
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dmaengine_terminate_all(chan);
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if (!data->error)
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data->error = -EIO;
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}
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if (data->flags & MMC_DATA_WRITE) {
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dir = DMA_TO_DEVICE;
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} else {
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dir = DMA_FROM_DEVICE;
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}
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dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
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/*
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* Use of DMA with scatter-gather is impossible.
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* Give up with DMA and switch back to PIO mode.
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*/
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if (status & MCI_RXDATAAVLBLMASK) {
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dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
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mmci_dma_release(host);
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}
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}
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static void mmci_dma_data_error(struct mmci_host *host)
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{
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dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
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dmaengine_terminate_all(host->dma_current);
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}
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static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
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{
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struct variant_data *variant = host->variant;
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struct dma_slave_config conf = {
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.src_addr = host->phybase + MMCIFIFO,
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.dst_addr = host->phybase + MMCIFIFO,
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.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
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.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
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.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
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};
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struct mmc_data *data = host->data;
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struct dma_chan *chan;
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struct dma_device *device;
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struct dma_async_tx_descriptor *desc;
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int nr_sg;
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host->dma_current = NULL;
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if (data->flags & MMC_DATA_READ) {
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conf.direction = DMA_FROM_DEVICE;
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chan = host->dma_rx_channel;
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} else {
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conf.direction = DMA_TO_DEVICE;
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chan = host->dma_tx_channel;
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}
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/* If there's no DMA channel, fall back to PIO */
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if (!chan)
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return -EINVAL;
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/* If less than or equal to the fifo size, don't bother with DMA */
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if (host->size <= variant->fifosize)
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return -EINVAL;
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device = chan->device;
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nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
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if (nr_sg == 0)
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return -EINVAL;
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dmaengine_slave_config(chan, &conf);
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desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
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conf.direction, DMA_CTRL_ACK);
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if (!desc)
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goto unmap_exit;
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/* Okay, go for it. */
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host->dma_current = chan;
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dev_vdbg(mmc_dev(host->mmc),
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"Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
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data->sg_len, data->blksz, data->blocks, data->flags);
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dmaengine_submit(desc);
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dma_async_issue_pending(chan);
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datactrl |= MCI_DPSM_DMAENABLE;
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/* Trigger the DMA transfer */
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writel(datactrl, host->base + MMCIDATACTRL);
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/*
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* Let the MMCI say when the data is ended and it's time
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* to fire next DMA request. When that happens, MMCI will
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* call mmci_data_end()
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*/
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writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
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host->base + MMCIMASK0);
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return 0;
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unmap_exit:
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dmaengine_terminate_all(chan);
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dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
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return -ENOMEM;
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}
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#else
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/* Blank functions if the DMA engine is not available */
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static inline void mmci_dma_setup(struct mmci_host *host)
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{
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}
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static inline void mmci_dma_release(struct mmci_host *host)
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{
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}
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static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
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{
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}
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static inline void mmci_dma_data_error(struct mmci_host *host)
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{
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}
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static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
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{
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return -ENOSYS;
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}
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#endif
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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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{
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struct variant_data *variant = host->variant;
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@ -201,8 +445,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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host->size = data->blksz * data->blocks;
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data->bytes_xfered = 0;
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mmci_init_sg(host, data);
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clks = (unsigned long long)data->timeout_ns * host->cclk;
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do_div(clks, 1000000000UL);
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@ -216,8 +458,21 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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BUG_ON(1 << blksz_bits != data->blksz);
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datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
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if (data->flags & MMC_DATA_READ) {
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if (data->flags & MMC_DATA_READ)
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datactrl |= MCI_DPSM_DIRECTION;
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/*
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* Attempt to use DMA operation mode, if this
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* should fail, fall back to PIO mode
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*/
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if (!mmci_dma_start_data(host, datactrl))
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return;
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/* IRQ mode, map the SG list for CPU reading/writing */
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mmci_init_sg(host, data);
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if (data->flags & MMC_DATA_READ) {
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irqmask = MCI_RXFIFOHALFFULLMASK;
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/*
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@ -281,6 +536,10 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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u32 remain, success;
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/* Terminate the DMA transfer */
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if (dma_inprogress(host))
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mmci_dma_data_error(host);
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/*
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* Calculate how far we are into the transfer. Note that
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* the data counter gives the number of bytes transferred
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@ -315,6 +574,8 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
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if (status & MCI_DATAEND || data->error) {
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if (dma_inprogress(host))
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mmci_dma_unmap(host, data);
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mmci_stop_data(host);
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if (!data->error)
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@ -767,6 +1028,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
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dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
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host->mclk);
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}
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host->phybase = dev->res.start;
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host->base = ioremap(dev->res.start, resource_size(&dev->res));
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if (!host->base) {
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ret = -ENOMEM;
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@ -894,9 +1156,12 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
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amba_set_drvdata(dev, mmc);
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dev_info(&dev->dev, "%s: PL%03x rev%u at 0x%08llx irq %d,%d\n",
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mmc_hostname(mmc), amba_part(dev), amba_rev(dev),
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(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
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dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
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mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
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amba_rev(dev), (unsigned long long)dev->res.start,
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dev->irq[0], dev->irq[1]);
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mmci_dma_setup(host);
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mmc_add_host(mmc);
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@ -943,6 +1208,7 @@ static int __devexit mmci_remove(struct amba_device *dev)
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writel(0, host->base + MMCICOMMAND);
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writel(0, host->base + MMCIDATACTRL);
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mmci_dma_release(host);
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free_irq(dev->irq[0], host);
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if (!host->singleirq)
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free_irq(dev->irq[1], host);
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@ -148,8 +148,10 @@
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struct clk;
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struct variant_data;
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struct dma_chan;
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struct mmci_host {
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phys_addr_t phybase;
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void __iomem *base;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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@ -179,5 +181,16 @@ struct mmci_host {
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struct sg_mapping_iter sg_miter;
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unsigned int size;
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struct regulator *vcc;
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#ifdef CONFIG_DMA_ENGINE
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/* DMA stuff */
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struct dma_chan *dma_current;
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struct dma_chan *dma_rx_channel;
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struct dma_chan *dma_tx_channel;
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#define dma_inprogress(host) ((host)->dma_current)
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#else
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#define dma_inprogress(host) (0)
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#endif
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};
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@ -6,6 +6,9 @@
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#include <linux/mmc/host.h>
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/* Just some dummy forwarding */
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struct dma_chan;
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/**
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* struct mmci_platform_data - platform configuration for the MMCI
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* (also known as PL180) block.
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@ -27,6 +30,17 @@
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* @cd_invert: true if the gpio_cd pin value is active low
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* @capabilities: the capabilities of the block as implemented in
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* this platform, signify anything MMC_CAP_* from mmc/host.h
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* @dma_filter: function used to select an apropriate RX and TX
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* DMA channel to be used for DMA, if and only if you're deploying the
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* generic DMA engine
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* @dma_rx_param: parameter passed to the DMA allocation
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* filter in order to select an apropriate RX channel. If
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* there is a bidirectional RX+TX channel, then just specify
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* this and leave dma_tx_param set to NULL
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* @dma_tx_param: parameter passed to the DMA allocation
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* filter in order to select an apropriate TX channel. If this
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* is NULL the driver will attempt to use the RX channel as a
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* bidirectional channel
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*/
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struct mmci_platform_data {
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unsigned int f_max;
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@ -38,6 +52,9 @@ struct mmci_platform_data {
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int gpio_cd;
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bool cd_invert;
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unsigned long capabilities;
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bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
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void *dma_rx_param;
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void *dma_tx_param;
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};
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#endif
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