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RDMA/mlx5: Add SQD2RTS bit to the alloc ucontext response

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The new bit in the comp_mask is needed to mark that kernel supports
SQD2RTS transition for the modify QP command.

Link: https://lore.kernel.org/r/7ce705fedac1b2b8e3a2f4013e04244dc5946344.1620641808.git.leonro@nvidia.com
Reviewed-by: Evgenii Kochetov <evgeniik@nvidia.com>
Signed-off-by: Sergey Gorenko <sergeygo@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Sergey Gorenko 2021-05-10 13:23:33 +03:00 committed by Jason Gunthorpe
parent 021c1f24f0
commit c906b86e9c
2 changed files with 5 additions and 0 deletions
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4
drivers/infiniband/hw/mlx5/main.c
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@ -1817,6 +1817,10 @@ static int set_ucontext_resp(struct ib_ucontext *uctx,
resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
return 0;
}

1
include/uapi/rdma/mlx5-abi.h
View File

@ -101,6 +101,7 @@ enum mlx5_ib_alloc_ucontext_resp_mask {
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2,
MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3,
};
enum mlx5_user_cmds_supp_uhw {