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clk: gcc-msm8996: Fix pcie 2 pipe register offset

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This patch corrects the register offset for pcie2 pipe clock.
Offset according to datasheet is 0x6e018 instead of 0x6e108.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: b1e010c0730a ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Srinivas Kandagatla 2016-08-25 12:20:46 +01:00 committed by Stephen Boyd
parent 6d91f2c014
commit ce61966c05
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/qcom/gcc-msm8996.c
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@ -2592,9 +2592,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
};
static struct clk_branch gcc_pcie_2_pipe_clk = {
.halt_reg = 0x6e108,
.halt_reg = 0x6e018,
.clkr = {
.enable_reg = 0x6e108,
.enable_reg = 0x6e018,
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_pipe_clk",