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ARM: dts: imx6sl: align pin config nodes with bindings

Browse Source 
Bindings for other NXP pin controllers expect pin configuration nodes in
pinctrl to match certain naming, so adjust these as well, even though
their bindings are not yet in dtschema format.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2024-09-02 13:40:39 +02:00 committed by Shawn Guo
parent a9c741d8e9
commit d1b4420366
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/boot/dts/nxp/imx/imx6sl-evk.dts
View File

@ -457,7 +457,7 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
@ -472,7 +472,7 @@ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
@ -498,7 +498,7 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
@ -509,7 +509,7 @@ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
@ -531,7 +531,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
@ -542,7 +542,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9

8
arch/arm/boot/dts/nxp/imx/imx6sl-warp.dts
View File

@ -166,7 +166,7 @@ MX6SL_PAD_SD2_RST__SD2_RESET 0x417059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
@ -182,7 +182,7 @@ MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
@ -209,7 +209,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
@ -220,7 +220,7 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9