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clk: divider: add CLK_DIVIDER_HIWORD_MASK flag

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In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds divider flag for this usage.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Haojian Zhuang 2013-06-08 22:47:18 +08:00 committed by Mike Turquette
parent ba492e9007
commit d57dfe7508
2 changed files with 18 additions and 2 deletions
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11
drivers/clk/clk-divider.c
View File

@ -227,8 +227,12 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
if (divider->lock) if (divider->lock)
spin_lock_irqsave(divider->lock, flags); spin_lock_irqsave(divider->lock, flags);
if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
val = div_mask(divider) << (divider->shift + 16);
} else {
val = readl(divider->reg); val = readl(divider->reg);
val &= ~(div_mask(divider) << divider->shift); val &= ~(div_mask(divider) << divider->shift);
}
val |= value << divider->shift; val |= value << divider->shift;
writel(val, divider->reg); writel(val, divider->reg);
@ -255,6 +259,13 @@ static struct clk *_register_divider(struct device *dev, const char *name,
struct clk *clk; struct clk *clk;
struct clk_init_data init; struct clk_init_data init;
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
if (width + shift > 16) {
pr_warn("divider value exceeds LOWORD field\n");
return ERR_PTR(-EINVAL);
}
}
/* allocate the divider */ /* allocate the divider */
div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
if (!div) { if (!div) {

5
include/linux/clk-provider.h
View File

@ -257,6 +257,10 @@ struct clk_div_table {
* Some hardware implementations gracefully handle this case and allow a * Some hardware implementations gracefully handle this case and allow a
* zero divisor by not modifying their input clock * zero divisor by not modifying their input clock
* (divide by one / bypass). * (divide by one / bypass).
* CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
* of this register, and mask of divider bits are in higher 16-bit of this
* register. While setting the divider bits, higher 16-bit should also be
* updated to indicate changing divider bits.
*/ */
struct clk_divider { struct clk_divider {
struct clk_hw hw; struct clk_hw hw;
@ -271,6 +275,7 @@ struct clk_divider {
#define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_ONE_BASED BIT(0)
#define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
#define CLK_DIVIDER_ALLOW_ZERO BIT(2) #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
#define CLK_DIVIDER_HIWORD_MASK BIT(3)
extern const struct clk_ops clk_divider_ops; extern const struct clk_ops clk_divider_ops;
struct clk *clk_register_divider(struct device *dev, const char *name, struct clk *clk_register_divider(struct device *dev, const char *name,