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net: renesas: rswitch: use FIELD_PREP for remaining MPIC register fields
Commit fb9e6039c3
("net: renesas: rswitch: fix initial MPIC register
setting") converted setting some MPIC fields to FIELD_PREP.
To keep common style, do the same with mii bus related fields of the
same register.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://patch.msgid.link/20241216071957.2587354-3-nikita.yoush@cogentembedded.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
206112fa65
commit
da75ba93e3
@ -1164,8 +1164,9 @@ static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
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static void rswitch_etha_enable_mii(struct rswitch_etha *etha)
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{
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rswitch_modify(etha->addr, MPIC, MPIC_PSMCS_MASK | MPIC_PSMHT_MASK,
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MPIC_PSMCS(etha->psmcs) | MPIC_PSMHT(0x06));
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rswitch_modify(etha->addr, MPIC, MPIC_PSMCS | MPIC_PSMHT,
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FIELD_PREP(MPIC_PSMCS, etha->psmcs) |
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FIELD_PREP(MPIC_PSMHT, 0x06));
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}
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static int rswitch_etha_hw_init(struct rswitch_etha *etha, const u8 *mac)
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@ -732,6 +732,8 @@ enum rswitch_etha_mode {
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#define MPIC_LSC_100M 1
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#define MPIC_LSC_1G 2
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#define MPIC_LSC_2_5G 3
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#define MPIC_PSMCS GENMASK(22, 16)
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#define MPIC_PSMHT GENMASK(26, 24)
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#define MDIO_READ_C45 0x03
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#define MDIO_WRITE_C45 0x01
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@ -747,14 +749,6 @@ enum rswitch_etha_mode {
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#define MMIS1_PRACS BIT(0) /* Read */
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#define MMIS1_CLEAR_FLAGS 0xf
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#define MPIC_PSMCS_SHIFT 16
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#define MPIC_PSMCS_MASK GENMASK(22, MPIC_PSMCS_SHIFT)
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#define MPIC_PSMCS(val) ((val) << MPIC_PSMCS_SHIFT)
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#define MPIC_PSMHT_SHIFT 24
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#define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)
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#define MPIC_PSMHT(val) ((val) << MPIC_PSMHT_SHIFT)
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#define MLVC_PLV BIT(16)
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/* GWCA */
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