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Merge branch 'add-the-dwmac-driver-support-for-t-head-th1520-soc'

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Drew Fustini says:

====================
Add the dwmac driver support for T-HEAD TH1520 SoC

This series adds support for dwmac gigabit ethernet in the T-Head TH1520
RISC-V SoC used on boards like BeagleV Ahead and the LicheePi 4A.

The gigabit ethernet on these boards does need pinctrl support to mux
the necessary pads. The pinctrl-th1520 driver, pinctrl binding, and
related dts patches are in linux-next. However, they are not yet in
net-next/main.

Therefore, I am dropping the dts patch for v5 as it will not build on
net-next/main due to the lack of the padctrl0_apsys pin controller node
in next-next/main version th1520.dtsi. It does exist in linux-next [1]
and the two patches in this series allow the ethernet ports to work
correctly on the LPi4A and Ahead when applied to linux-next.

The dwmac-thead driver in this series does not need the pinctrl-th1520
driver to build. Nor does the thead,th1520-gmac.yaml binding need the
pinctrl binding to pass the schema check.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/riscv/boot/dts/thead/th1520.dtsi
====================

Link: https://patch.msgid.link/20241103-th1520-gmac-v7-0-ef094a30169c@tenstorrent.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2024-11-05 17:49:22 -08:00
commit dc0f314bc9
6 changed files with 397 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/net/snps,dwmac.yaml
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@ -101,6 +101,7 @@ properties:
- snps,dwxgmac-2.10
- starfive,jh7100-dwmac
- starfive,jh7110-dwmac
- thead,th1520-gmac
reg:
minItems: 1

110
Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml Normal file
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@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/thead,th1520-gmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-HEAD TH1520 GMAC Ethernet controller
maintainers:
- Drew Fustini <dfustini@tenstorrent.com>
description: |
The TH1520 GMAC is described in the TH1520 Peripheral Interface User Manual
https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Features include
- Compliant with IEEE802.3 Specification
- IEEE 1588-2008 standard for precision networked clock synchronization
- Supports 10/100/1000Mbps data transfer rate
- Supports RGMII/MII interface
- Preamble and start of frame data (SFD) insertion in Transmit path
- Preamble and SFD deletion in the Receive path
- Automatic CRC and pad generation options for receive frames
- MDIO master interface for PHY device configuration and management
The GMAC Registers consists of two parts
- APB registers are used to configure clock frequency/clock enable/clock
direction/PHY interface type.
- AHB registers are use to configure GMAC core (DesignWare Core part).
GMAC core register consists of DMA registers and GMAC registers.
select:
properties:
compatible:
contains:
enum:
- thead,th1520-gmac
required:
- compatible
allOf:
- $ref: snps,dwmac.yaml#
properties:
compatible:
items:
- enum:
- thead,th1520-gmac
- const: snps,dwmac-3.70a
reg:
items:
- description: DesignWare GMAC IP core registers
- description: GMAC APB registers
reg-names:
items:
- const: dwmac
- const: apb
clocks:
items:
- description: GMAC main clock
- description: Peripheral registers interface clock
clock-names:
items:
- const: stmmaceth
- const: pclk
interrupts:
items:
- description: Combined signal for various interrupt events
interrupt-names:
items:
- const: macirq
required:
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
gmac0: ethernet@e7070000 {
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
reg = <0xe7070000 0x2000>, <0xec003000 0x1000>;
reg-names = "dwmac", "apb";
clocks = <&clk 1>, <&clk 2>;
clock-names = "stmmaceth", "pclk";
interrupts = <66>;
interrupt-names = "macirq";
phy-mode = "rgmii-id";
snps,fixed-burst;
snps,axi-config = <&stmmac_axi_setup>;
snps,pbl = <32>;
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

2
MAINTAINERS
View File

@ -19845,8 +19845,10 @@ L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/pdp7/linux.git
F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
F: Documentation/devicetree/bindings/net/thead,th1520-gmac.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
RNBD BLOCK DRIVERS

10
drivers/net/ethernet/stmicro/stmmac/Kconfig
View File

@ -228,6 +228,16 @@ config DWMAC_SUN8I
stmmac device driver. This driver is used for H3/A83T/A64
EMAC ethernet controller.
config DWMAC_THEAD
tristate "T-HEAD dwmac support"
depends on OF && (ARCH_THEAD || COMPILE_TEST)
help
Support for ethernet controllers on T-HEAD RISC-V SoCs
This selects the T-HEAD platform specific glue layer support for
the stmmac device driver. This driver is used for T-HEAD TH1520
ethernet controller.
config DWMAC_IMX8
tristate "NXP IMX8 DWMAC support"
default ARCH_MXC

1
drivers/net/ethernet/stmicro/stmmac/Makefile
View File

@ -28,6 +28,7 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o
obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o
obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o
obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o
obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o
obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o
obj-$(CONFIG_DWMAC_LOONGSON1) += dwmac-loongson1.o

273
drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c Normal file
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@ -0,0 +1,273 @@
// SPDX-License-Identifier: GPL-2.0
/*
* T-HEAD DWMAC platform driver
*
* Copyright (C) 2021 Alibaba Group Holding Limited.
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*
*/
#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_net.h>
#include <linux/platform_device.h>
#include "stmmac_platform.h"
#define GMAC_CLK_EN 0x00
#define GMAC_TX_CLK_EN BIT(1)
#define GMAC_TX_CLK_N_EN BIT(2)
#define GMAC_TX_CLK_OUT_EN BIT(3)
#define GMAC_RX_CLK_EN BIT(4)
#define GMAC_RX_CLK_N_EN BIT(5)
#define GMAC_EPHY_REF_CLK_EN BIT(6)
#define GMAC_RXCLK_DELAY_CTRL 0x04
#define GMAC_RXCLK_BYPASS BIT(15)
#define GMAC_RXCLK_INVERT BIT(14)
#define GMAC_RXCLK_DELAY GENMASK(4, 0)
#define GMAC_TXCLK_DELAY_CTRL 0x08
#define GMAC_TXCLK_BYPASS BIT(15)
#define GMAC_TXCLK_INVERT BIT(14)
#define GMAC_TXCLK_DELAY GENMASK(4, 0)
#define GMAC_PLLCLK_DIV 0x0c
#define GMAC_PLLCLK_DIV_EN BIT(31)
#define GMAC_PLLCLK_DIV_NUM GENMASK(7, 0)
#define GMAC_GTXCLK_SEL 0x18
#define GMAC_GTXCLK_SEL_PLL BIT(0)
#define GMAC_INTF_CTRL 0x1c
#define PHY_INTF_MASK BIT(0)
#define PHY_INTF_RGMII FIELD_PREP(PHY_INTF_MASK, 1)
#define PHY_INTF_MII_GMII FIELD_PREP(PHY_INTF_MASK, 0)
#define GMAC_TXCLK_OEN 0x20
#define TXCLK_DIR_MASK BIT(0)
#define TXCLK_DIR_OUTPUT FIELD_PREP(TXCLK_DIR_MASK, 0)
#define TXCLK_DIR_INPUT FIELD_PREP(TXCLK_DIR_MASK, 1)
#define GMAC_GMII_RGMII_RATE 125000000
#define GMAC_MII_RATE 25000000
struct thead_dwmac {
struct plat_stmmacenet_data *plat;
void __iomem *apb_base;
struct device *dev;
};
static int thead_dwmac_set_phy_if(struct plat_stmmacenet_data *plat)
{
struct thead_dwmac *dwmac = plat->bsp_priv;
u32 phyif;
switch (plat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
phyif = PHY_INTF_MII_GMII;
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
phyif = PHY_INTF_RGMII;
break;
default:
dev_err(dwmac->dev, "unsupported phy interface %d\n",
plat->mac_interface);
return -EINVAL;
}
writel(phyif, dwmac->apb_base + GMAC_INTF_CTRL);
return 0;
}
static int thead_dwmac_set_txclk_dir(struct plat_stmmacenet_data *plat)
{
struct thead_dwmac *dwmac = plat->bsp_priv;
u32 txclk_dir;
switch (plat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
txclk_dir = TXCLK_DIR_INPUT;
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
txclk_dir = TXCLK_DIR_OUTPUT;
break;
default:
dev_err(dwmac->dev, "unsupported phy interface %d\n",
plat->mac_interface);
return -EINVAL;
}
writel(txclk_dir, dwmac->apb_base + GMAC_TXCLK_OEN);
return 0;
}
static void thead_dwmac_fix_speed(void *priv, unsigned int speed, unsigned int mode)
{
struct plat_stmmacenet_data *plat;
struct thead_dwmac *dwmac = priv;
unsigned long rate;
u32 div, reg;
plat = dwmac->plat;
switch (plat->mac_interface) {
/* For MII, rxc/txc is provided by phy */
case PHY_INTERFACE_MODE_MII:
return;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
rate = clk_get_rate(plat->stmmac_clk);
if (!rate || rate % GMAC_GMII_RGMII_RATE != 0 ||
rate % GMAC_MII_RATE != 0) {
dev_err(dwmac->dev, "invalid gmac rate %ld\n", rate);
return;
}
writel(0, dwmac->apb_base + GMAC_PLLCLK_DIV);
switch (speed) {
case SPEED_1000:
div = rate / GMAC_GMII_RGMII_RATE;
break;
case SPEED_100:
div = rate / GMAC_MII_RATE;
break;
case SPEED_10:
div = rate * 10 / GMAC_MII_RATE;
break;
default:
dev_err(dwmac->dev, "invalid speed %u\n", speed);
return;
}
reg = FIELD_PREP(GMAC_PLLCLK_DIV_EN, 1) |
FIELD_PREP(GMAC_PLLCLK_DIV_NUM, div);
writel(reg, dwmac->apb_base + GMAC_PLLCLK_DIV);
break;
default:
dev_err(dwmac->dev, "unsupported phy interface %d\n",
plat->mac_interface);
return;
}
}
static int thead_dwmac_enable_clk(struct plat_stmmacenet_data *plat)
{
struct thead_dwmac *dwmac = plat->bsp_priv;
u32 reg;
switch (plat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
reg = GMAC_RX_CLK_EN | GMAC_TX_CLK_EN;
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* use pll */
writel(GMAC_GTXCLK_SEL_PLL, dwmac->apb_base + GMAC_GTXCLK_SEL);
reg = GMAC_TX_CLK_EN | GMAC_TX_CLK_N_EN | GMAC_TX_CLK_OUT_EN |
GMAC_RX_CLK_EN | GMAC_RX_CLK_N_EN;
break;
default:
dev_err(dwmac->dev, "unsupported phy interface %d\n",
plat->mac_interface);
return -EINVAL;
}
writel(reg, dwmac->apb_base + GMAC_CLK_EN);
return 0;
}
static int thead_dwmac_init(struct platform_device *pdev, void *priv)
{
struct thead_dwmac *dwmac = priv;
unsigned int reg;
int ret;
ret = thead_dwmac_set_phy_if(dwmac->plat);
if (ret)
return ret;
ret = thead_dwmac_set_txclk_dir(dwmac->plat);
if (ret)
return ret;
reg = readl(dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);
reg &= ~(GMAC_RXCLK_DELAY);
reg |= FIELD_PREP(GMAC_RXCLK_DELAY, 0);
writel(reg, dwmac->apb_base + GMAC_RXCLK_DELAY_CTRL);
reg = readl(dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);
reg &= ~(GMAC_TXCLK_DELAY);
reg |= FIELD_PREP(GMAC_TXCLK_DELAY, 0);
writel(reg, dwmac->apb_base + GMAC_TXCLK_DELAY_CTRL);
return thead_dwmac_enable_clk(dwmac->plat);
}
static int thead_dwmac_probe(struct platform_device *pdev)
{
struct stmmac_resources stmmac_res;
struct plat_stmmacenet_data *plat;
struct thead_dwmac *dwmac;
void __iomem *apb;
int ret;
ret = stmmac_get_platform_resources(pdev, &stmmac_res);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"failed to get resources\n");
plat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac);
if (IS_ERR(plat))
return dev_err_probe(&pdev->dev, PTR_ERR(plat),
"dt configuration failed\n");
dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
if (!dwmac)
return -ENOMEM;
apb = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(apb))
return dev_err_probe(&pdev->dev, PTR_ERR(apb),
"failed to remap gmac apb registers\n");
dwmac->dev = &pdev->dev;
dwmac->plat = plat;
dwmac->apb_base = apb;
plat->bsp_priv = dwmac;
plat->fix_mac_speed = thead_dwmac_fix_speed;
plat->init = thead_dwmac_init;
return devm_stmmac_pltfr_probe(pdev, plat, &stmmac_res);
}
static const struct of_device_id thead_dwmac_match[] = {
{ .compatible = "thead,th1520-gmac" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, thead_dwmac_match);
static struct platform_driver thead_dwmac_driver = {
.probe = thead_dwmac_probe,
.driver = {
.name = "thead-dwmac",
.pm = &stmmac_pltfr_pm_ops,
.of_match_table = thead_dwmac_match,
},
};
module_platform_driver(thead_dwmac_driver);
MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
MODULE_AUTHOR("Drew Fustini <drew@pdp7.com>");
MODULE_DESCRIPTION("T-HEAD DWMAC platform driver");
MODULE_LICENSE("GPL");