mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-08 23:12:03 +00:00
Merge remote-tracking branch 'torvalds/master' into perf/core
To pick up fixes. Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Arnaldo Carvalho de Melo
commit
debe70e488
@ -176,3 +176,9 @@ Contact: Keith Busch <keith.busch@intel.com>
|
||||
Description:
|
||||
The cache write policy: 0 for write-back, 1 for write-through,
|
||||
other or unknown.
|
||||
|
||||
What: /sys/devices/system/node/nodeX/x86/sgx_total_bytes
|
||||
Date: November 2021
|
||||
Contact: Jarkko Sakkinen <jarkko@kernel.org>
|
||||
Description:
|
||||
The total amount of SGX physical memory in bytes.
|
||||
|
||||
@ -734,10 +734,9 @@ SecurityFlags Flags which control security negotiation and
|
||||
using weaker password hashes is 0x37037 (lanman,
|
||||
plaintext, ntlm, ntlmv2, signing allowed). Some
|
||||
SecurityFlags require the corresponding menuconfig
|
||||
options to be enabled (lanman and plaintext require
|
||||
CONFIG_CIFS_WEAK_PW_HASH for example). Enabling
|
||||
plaintext authentication currently requires also
|
||||
enabling lanman authentication in the security flags
|
||||
options to be enabled. Enabling plaintext
|
||||
authentication currently requires also enabling
|
||||
lanman authentication in the security flags
|
||||
because the cifs module only supports sending
|
||||
laintext passwords using the older lanman dialect
|
||||
form of the session setup SMB. (e.g. for authentication
|
||||
|
||||
@ -2339,13 +2339,7 @@
|
||||
disks (see major number 3) except that the limit on
|
||||
partitions is 31.
|
||||
|
||||
162 char Raw block device interface
|
||||
0 = /dev/rawctl Raw I/O control device
|
||||
1 = /dev/raw/raw1 First raw I/O device
|
||||
2 = /dev/raw/raw2 Second raw I/O device
|
||||
...
|
||||
max minor number of raw device is set by kernel config
|
||||
MAX_RAW_DEVS or raw module parameter 'max_raw_devs'
|
||||
162 char Used for (now removed) raw block device interface
|
||||
|
||||
163 char
|
||||
|
||||
|
||||
@ -2940,7 +2940,7 @@
|
||||
both parameters are enabled, hugetlb_free_vmemmap takes
|
||||
precedence over memory_hotplug.memmap_on_memory.
|
||||
|
||||
memtest= [KNL,X86,ARM,PPC,RISCV] Enable memtest
|
||||
memtest= [KNL,X86,ARM,M68K,PPC,RISCV] Enable memtest
|
||||
Format: <integer>
|
||||
default : 0 <disable>
|
||||
Specifies the number of memtest passes to be
|
||||
|
||||
106
Documentation/admin-guide/perf/hisi-pcie-pmu.rst
Normal file
106
Documentation/admin-guide/perf/hisi-pcie-pmu.rst
Normal file
@ -0,0 +1,106 @@
|
||||
================================================
|
||||
HiSilicon PCIe Performance Monitoring Unit (PMU)
|
||||
================================================
|
||||
|
||||
On Hip09, HiSilicon PCIe Performance Monitoring Unit (PMU) could monitor
|
||||
bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
|
||||
|
||||
Each PCIe Core has a PMU to monitor multi Root Ports of this PCIe Core and
|
||||
all Endpoints downstream these Root Ports.
|
||||
|
||||
|
||||
HiSilicon PCIe PMU driver
|
||||
=========================
|
||||
|
||||
The PCIe PMU driver registers a perf PMU with the name of its sicl-id and PCIe
|
||||
Core id.::
|
||||
|
||||
/sys/bus/event_source/hisi_pcie<sicl>_<core>
|
||||
|
||||
PMU driver provides description of available events and filter options in sysfs,
|
||||
see /sys/bus/event_source/devices/hisi_pcie<sicl>_<core>.
|
||||
|
||||
The "format" directory describes all formats of the config (events) and config1
|
||||
(filter options) fields of the perf_event_attr structure. The "events" directory
|
||||
describes all documented events shown in perf list.
|
||||
|
||||
The "identifier" sysfs file allows users to identify the version of the
|
||||
PMU hardware device.
|
||||
|
||||
The "bus" sysfs file allows users to get the bus number of Root Ports
|
||||
monitored by PMU.
|
||||
|
||||
Example usage of perf::
|
||||
|
||||
$# perf list
|
||||
hisi_pcie0_0/rx_mwr_latency/ [kernel PMU event]
|
||||
hisi_pcie0_0/rx_mwr_cnt/ [kernel PMU event]
|
||||
------------------------------------------
|
||||
|
||||
$# perf stat -e hisi_pcie0_0/rx_mwr_latency/
|
||||
$# perf stat -e hisi_pcie0_0/rx_mwr_cnt/
|
||||
$# perf stat -g -e hisi_pcie0_0/rx_mwr_latency/ -e hisi_pcie0_0/rx_mwr_cnt/
|
||||
|
||||
The current driver does not support sampling. So "perf record" is unsupported.
|
||||
Also attach to a task is unsupported for PCIe PMU.
|
||||
|
||||
Filter options
|
||||
--------------
|
||||
|
||||
1. Target filter
|
||||
PMU could only monitor the performance of traffic downstream target Root Ports
|
||||
or downstream target Endpoint. PCIe PMU driver support "port" and "bdf"
|
||||
interfaces for users, and these two interfaces aren't supported at the same
|
||||
time.
|
||||
|
||||
-port
|
||||
"port" filter can be used in all PCIe PMU events, target Root Port can be
|
||||
selected by configuring the 16-bits-bitmap "port". Multi ports can be selected
|
||||
for AP-layer-events, and only one port can be selected for TL/DL-layer-events.
|
||||
|
||||
For example, if target Root Port is 0000:00:00.0 (x8 lanes), bit0 of bitmap
|
||||
should be set, port=0x1; if target Root Port is 0000:00:04.0 (x4 lanes),
|
||||
bit8 is set, port=0x100; if these two Root Ports are both monitored, port=0x101.
|
||||
|
||||
Example usage of perf::
|
||||
|
||||
$# perf stat -e hisi_pcie0_0/rx_mwr_latency,port=0x1/ sleep 5
|
||||
|
||||
-bdf
|
||||
|
||||
"bdf" filter can only be used in bandwidth events, target Endpoint is selected
|
||||
by configuring BDF to "bdf". Counter only counts the bandwidth of message
|
||||
requested by target Endpoint.
|
||||
|
||||
For example, "bdf=0x3900" means BDF of target Endpoint is 0000:39:00.0.
|
||||
|
||||
Example usage of perf::
|
||||
|
||||
$# perf stat -e hisi_pcie0_0/rx_mrd_flux,bdf=0x3900/ sleep 5
|
||||
|
||||
2. Trigger filter
|
||||
Event statistics start when the first time TLP length is greater/smaller
|
||||
than trigger condition. You can set the trigger condition by writing "trig_len",
|
||||
and set the trigger mode by writing "trig_mode". This filter can only be used
|
||||
in bandwidth events.
|
||||
|
||||
For example, "trig_len=4" means trigger condition is 2^4 DW, "trig_mode=0"
|
||||
means statistics start when TLP length > trigger condition, "trig_mode=1"
|
||||
means start when TLP length < condition.
|
||||
|
||||
Example usage of perf::
|
||||
|
||||
$# perf stat -e hisi_pcie0_0/rx_mrd_flux,trig_len=0x4,trig_mode=1/ sleep 5
|
||||
|
||||
3. Threshold filter
|
||||
Counter counts when TLP length within the specified range. You can set the
|
||||
threshold by writing "thr_len", and set the threshold mode by writing
|
||||
"thr_mode". This filter can only be used in bandwidth events.
|
||||
|
||||
For example, "thr_len=4" means threshold is 2^4 DW, "thr_mode=0" means
|
||||
counter counts when TLP length >= threshold, and "thr_mode=1" means counts
|
||||
when TLP length < threshold.
|
||||
|
||||
Example usage of perf::
|
||||
|
||||
$# perf stat -e hisi_pcie0_0/rx_mrd_flux,thr_len=0x4,thr_mode=1/ sleep 5
|
||||
@ -905,6 +905,17 @@ enabled, otherwise writing to this file will return ``-EBUSY``.
|
||||
The default value is 8.
|
||||
|
||||
|
||||
perf_user_access (arm64 only)
|
||||
=================================
|
||||
|
||||
Controls user space access for reading perf event counters. When set to 1,
|
||||
user space can read performance monitor counter registers directly.
|
||||
|
||||
The default value is 0 (access disabled).
|
||||
|
||||
See Documentation/arm64/perf.rst for more information.
|
||||
|
||||
|
||||
pid_max
|
||||
=======
|
||||
|
||||
|
||||
@ -275,6 +275,23 @@ infrastructure:
|
||||
| SVEVer | [3-0] | y |
|
||||
+------------------------------+---------+---------+
|
||||
|
||||
8) ID_AA64MMFR1_EL1 - Memory model feature register 1
|
||||
|
||||
+------------------------------+---------+---------+
|
||||
| Name | bits | visible |
|
||||
+------------------------------+---------+---------+
|
||||
| AFP | [47-44] | y |
|
||||
+------------------------------+---------+---------+
|
||||
|
||||
9) ID_AA64ISAR2_EL1 - Instruction set attribute register 2
|
||||
|
||||
+------------------------------+---------+---------+
|
||||
| Name | bits | visible |
|
||||
+------------------------------+---------+---------+
|
||||
| RPRES | [7-4] | y |
|
||||
+------------------------------+---------+---------+
|
||||
|
||||
|
||||
Appendix I: Example
|
||||
-------------------
|
||||
|
||||
|
||||
@ -251,6 +251,14 @@ HWCAP2_ECV
|
||||
|
||||
Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
|
||||
|
||||
HWCAP2_AFP
|
||||
|
||||
Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
|
||||
|
||||
HWCAP2_RPRES
|
||||
|
||||
Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
|
||||
|
||||
4. Unused AT_HWCAP bits
|
||||
-----------------------
|
||||
|
||||
|
||||
@ -2,7 +2,10 @@
|
||||
|
||||
.. _perf_index:
|
||||
|
||||
=====================
|
||||
====
|
||||
Perf
|
||||
====
|
||||
|
||||
Perf Event Attributes
|
||||
=====================
|
||||
|
||||
@ -88,3 +91,76 @@ exclude_host. However when using !exclude_hv there is a small blackout
|
||||
window at the guest entry/exit where host events are not captured.
|
||||
|
||||
On VHE systems there are no blackout windows.
|
||||
|
||||
Perf Userspace PMU Hardware Counter Access
|
||||
==========================================
|
||||
|
||||
Overview
|
||||
--------
|
||||
The perf userspace tool relies on the PMU to monitor events. It offers an
|
||||
abstraction layer over the hardware counters since the underlying
|
||||
implementation is cpu-dependent.
|
||||
Arm64 allows userspace tools to have access to the registers storing the
|
||||
hardware counters' values directly.
|
||||
|
||||
This targets specifically self-monitoring tasks in order to reduce the overhead
|
||||
by directly accessing the registers without having to go through the kernel.
|
||||
|
||||
How-to
|
||||
------
|
||||
The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu
|
||||
registers is enabled and that the userspace has access to the relevant
|
||||
information in order to use them.
|
||||
|
||||
In order to have access to the hardware counters, the global sysctl
|
||||
kernel/perf_user_access must first be enabled:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
echo 1 > /proc/sys/kernel/perf_user_access
|
||||
|
||||
It is necessary to open the event using the perf tool interface with config1:1
|
||||
attr bit set: the sys_perf_event_open syscall returns a fd which can
|
||||
subsequently be used with the mmap syscall in order to retrieve a page of memory
|
||||
containing information about the event. The PMU driver uses this page to expose
|
||||
to the user the hardware counter's index and other necessary data. Using this
|
||||
index enables the user to access the PMU registers using the `mrs` instruction.
|
||||
Access to the PMU registers is only valid while the sequence lock is unchanged.
|
||||
In particular, the PMSELR_EL0 register is zeroed each time the sequence lock is
|
||||
changed.
|
||||
|
||||
The userspace access is supported in libperf using the perf_evsel__mmap()
|
||||
and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for
|
||||
an example.
|
||||
|
||||
About heterogeneous systems
|
||||
---------------------------
|
||||
On heterogeneous systems such as big.LITTLE, userspace PMU counter access can
|
||||
only be enabled when the tasks are pinned to a homogeneous subset of cores and
|
||||
the corresponding PMU instance is opened by specifying the 'type' attribute.
|
||||
The use of generic event types is not supported in this case.
|
||||
|
||||
Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It
|
||||
can be run using the perf tool to check that the access to the registers works
|
||||
correctly from userspace:
|
||||
|
||||
.. code-block:: sh
|
||||
|
||||
perf test -v user
|
||||
|
||||
About chained events and counter sizes
|
||||
--------------------------------------
|
||||
The user can request either a 32-bit (config1:0 == 0) or 64-bit (config1:0 == 1)
|
||||
counter along with userspace access. The sys_perf_event_open syscall will fail
|
||||
if a 64-bit counter is requested and the hardware doesn't support 64-bit
|
||||
counters. Chained events are not supported in conjunction with userspace counter
|
||||
access. If a 32-bit counter is requested on hardware with 64-bit counters, then
|
||||
userspace must treat the upper 32-bits read from the counter as UNKNOWN. The
|
||||
'pmc_width' field in the user page will indicate the valid width of the counter
|
||||
and should be used to mask the upper bits as needed.
|
||||
|
||||
.. Links
|
||||
.. _tools/perf/arch/arm64/tests/user-events.c:
|
||||
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c
|
||||
.. _tools/lib/perf/tests/test-evsel.c:
|
||||
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/lib/perf/tests/test-evsel.c
|
||||
|
||||
@ -255,7 +255,7 @@ prctl(PR_SVE_GET_VL)
|
||||
vector length change (which would only normally be the case between a
|
||||
fork() or vfork() and the corresponding execve() in typical use).
|
||||
|
||||
To extract the vector length from the result, and it with
|
||||
To extract the vector length from the result, bitwise and it with
|
||||
PR_SVE_VL_LEN_MASK.
|
||||
|
||||
Return value: a nonnegative value on success, or a negative value on error:
|
||||
|
||||
@ -49,7 +49,7 @@ how the user addresses are used by the kernel:
|
||||
|
||||
- ``brk()``, ``mmap()`` and the ``new_address`` argument to
|
||||
``mremap()`` as these have the potential to alias with existing
|
||||
user addresses.
|
||||
user addresses.
|
||||
|
||||
NOTE: This behaviour changed in v5.6 and so some earlier kernels may
|
||||
incorrectly accept valid tagged pointers for the ``brk()``,
|
||||
|
||||
@ -12,12 +12,19 @@ maintainers:
|
||||
description: |
|
||||
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
|
||||
|
||||
This currently includes devices based on the "M1" SoC, starting with the
|
||||
three Mac models released in late 2020:
|
||||
This currently includes devices based on the "M1" SoC:
|
||||
|
||||
- Mac mini (M1, 2020)
|
||||
- MacBook Pro (13-inch, M1, 2020)
|
||||
- MacBook Air (M1, 2020)
|
||||
- iMac (24-inch, M1, 2021)
|
||||
|
||||
And devices based on the "M1 Pro" and "M1 Max" SoCs:
|
||||
|
||||
- MacBook Pro (14-inch, M1 Pro, 2021)
|
||||
- MacBook Pro (14-inch, M1 Max, 2021)
|
||||
- MacBook Pro (16-inch, M1 Pro, 2021)
|
||||
- MacBook Pro (16-inch, M1 Max, 2021)
|
||||
|
||||
The compatible property should follow this format:
|
||||
|
||||
@ -56,8 +63,24 @@ properties:
|
||||
- apple,j274 # Mac mini (M1, 2020)
|
||||
- apple,j293 # MacBook Pro (13-inch, M1, 2020)
|
||||
- apple,j313 # MacBook Air (M1, 2020)
|
||||
- apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
|
||||
- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
|
||||
- const: apple,t8103
|
||||
- const: apple,arm-platform
|
||||
- description: Apple M1 Pro SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
|
||||
- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
|
||||
- const: apple,t6000
|
||||
- const: apple,arm-platform
|
||||
- description: Apple M1 Max SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
|
||||
- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
|
||||
- const: apple,t6001
|
||||
- const: apple,arm-platform
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
|
||||
134
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
Normal file
134
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
Normal file
@ -0,0 +1,134 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoC Power Manager (PMGR)
|
||||
|
||||
maintainers:
|
||||
- Hector Martin <marcan@marcan.st>
|
||||
|
||||
description: |
|
||||
Apple SoCs include PMGR blocks responsible for power management,
|
||||
which can control various clocks, resets, power states, and
|
||||
performance features. This node represents the PMGR as a syscon,
|
||||
with sub-nodes representing individual features.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^power-management@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,t8103-pmgr
|
||||
- apple,t6000-pmgr
|
||||
- const: apple,pmgr
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"power-controller@[0-9a-f]+$":
|
||||
description:
|
||||
The individual power management domains within this controller
|
||||
type: object
|
||||
$ref: /power/apple,pmgr-pwrstate.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
power-management@23b700000 {
|
||||
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x3b700000 0x0 0x14000>;
|
||||
|
||||
ps_sio: power-controller@1c0 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x1c0 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "sio";
|
||||
apple,always-on;
|
||||
};
|
||||
|
||||
ps_uart_p: power-controller@220 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x220 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "uart_p";
|
||||
power-domains = <&ps_sio>;
|
||||
};
|
||||
|
||||
ps_uart0: power-controller@270 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x270 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "uart0";
|
||||
power-domains = <&ps_uart_p>;
|
||||
};
|
||||
};
|
||||
|
||||
power-management@23d280000 {
|
||||
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2 0x3d280000 0x0 0xc000>;
|
||||
|
||||
ps_aop_filter: power-controller@4000 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x4000 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "aop_filter";
|
||||
};
|
||||
|
||||
ps_aop_base: power-controller@4010 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x4010 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "aop_base";
|
||||
power-domains = <&ps_aop_filter>;
|
||||
};
|
||||
|
||||
ps_aop_shim: power-controller@4038 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x4038 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "aop_shim";
|
||||
power-domains = <&ps_aop_base>;
|
||||
};
|
||||
|
||||
ps_aop_uart0: power-controller@4048 {
|
||||
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
|
||||
reg = <0x4048 8>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <0>;
|
||||
label = "aop_uart0";
|
||||
power-domains = <&ps_aop_shim>;
|
||||
};
|
||||
};
|
||||
};
|
||||
37
Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml
Normal file
37
Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml
Normal file
@ -0,0 +1,37 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
|
||||
# Copyright 2021 Joel Stanley, IBM Corp.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: ASPEED Secure Boot Controller
|
||||
|
||||
maintainers:
|
||||
- Joel Stanley <joel@jms.id.au>
|
||||
- Andrew Jeffery <andrew@aj.id.au>
|
||||
|
||||
description: |
|
||||
The ASPEED SoCs have a register bank for interacting with the secure boot
|
||||
controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: aspeed,ast2600-sbc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sbc: secure-boot-controller@1e6f2000 {
|
||||
compatible = "aspeed,ast2600-sbc";
|
||||
reg = <0x1e6f2000 0x1000>;
|
||||
};
|
||||
@ -29,6 +29,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- asus,gt-ac5300
|
||||
- netgear,raxe500
|
||||
- const: brcm,bcm4908
|
||||
|
||||
- description: BCM49408 based boards
|
||||
|
||||
@ -174,6 +174,7 @@ properties:
|
||||
- qcom,kryo560
|
||||
- qcom,kryo570
|
||||
- qcom,kryo685
|
||||
- qcom,kryo780
|
||||
- qcom,scorpion
|
||||
|
||||
enable-method:
|
||||
|
||||
@ -24,6 +24,12 @@ properties:
|
||||
compatible:
|
||||
const: linaro,optee-tz
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: |
|
||||
This interrupt which is used to signal an event by the secure world
|
||||
software is expected to be edge-triggered.
|
||||
|
||||
method:
|
||||
enum: [smc, hvc]
|
||||
description: |
|
||||
@ -42,10 +48,12 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -240,6 +240,7 @@ properties:
|
||||
- uniwest,imx6q-evi # Uniwest Evi
|
||||
- variscite,dt6customboard
|
||||
- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
|
||||
- ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board
|
||||
- zealz,imx6q-gk802 # Zealz GK802
|
||||
- zii,imx6q-zii-rdu2 # ZII RDU2 Board
|
||||
- const: fsl,imx6q
|
||||
@ -323,6 +324,20 @@ properties:
|
||||
- const: toradex,apalis_imx6q
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6q-mba6x-a
|
||||
- const: tq,mba6a # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6q-tqma6q-a
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6q-mba6x-b
|
||||
- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6q-tqma6q-b
|
||||
- const: fsl,imx6q
|
||||
|
||||
- description: i.MX6QP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -334,6 +349,7 @@ properties:
|
||||
- kvg,vicutp # Kverneland UT1P board
|
||||
- prt,prtwd3 # Protonic WD3 board
|
||||
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
|
||||
- ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board
|
||||
- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
|
||||
- const: fsl,imx6qp
|
||||
|
||||
@ -344,6 +360,13 @@ properties:
|
||||
- const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: TQ-Systems TQMa6QP SoM on MBa6x
|
||||
items:
|
||||
- const: tq,imx6qp-mba6x-b
|
||||
- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6qp-tqma6qp-b
|
||||
- const: fsl,imx6qp
|
||||
|
||||
- description: i.MX6DL based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -482,6 +505,20 @@ properties:
|
||||
- const: dh,imx6s-dhcom-som
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6dl-mba6x-a
|
||||
- const: tq,mba6a # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6dl-tqma6dl-a
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x
|
||||
items:
|
||||
- const: tq,imx6dl-mba6x-b
|
||||
- const: tq,mba6b # Expected by bootloader, to be removed in the future
|
||||
- const: tq,imx6dl-tqma6dl-b
|
||||
- const: fsl,imx6dl
|
||||
|
||||
- description: i.MX6SL based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -580,6 +617,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- joz,jozacp # JOZ Access Point
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
|
||||
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
|
||||
@ -632,6 +670,7 @@ properties:
|
||||
- description: i.MX6ULZ based Boards
|
||||
items:
|
||||
- enum:
|
||||
- bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster
|
||||
- fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
|
||||
- const: fsl,imx6ull # This seems odd. Should be last?
|
||||
- const: fsl,imx6ulz
|
||||
@ -754,10 +793,23 @@ properties:
|
||||
- const: variscite,var-som-mx8mm
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description:
|
||||
TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip
|
||||
variants. It is designed to be soldered on different carrier boards.
|
||||
All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only
|
||||
one compatible is needed.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx
|
||||
- const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM
|
||||
- const: fsl,imx8mm
|
||||
|
||||
- description: i.MX8MN based Boards
|
||||
items:
|
||||
- enum:
|
||||
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
|
||||
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
|
||||
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
|
||||
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
|
||||
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
|
||||
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
|
||||
@ -769,6 +821,17 @@ properties:
|
||||
- const: variscite,var-som-mx8mn
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description:
|
||||
TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip
|
||||
variants. It is designed to be soldered on different carrier boards.
|
||||
All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only
|
||||
one compatible is needed.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx
|
||||
- const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM
|
||||
- const: fsl,imx8mn
|
||||
|
||||
- description: i.MX8MP based Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -805,6 +868,15 @@ properties:
|
||||
- const: purism,librem5
|
||||
- const: fsl,imx8mq
|
||||
|
||||
- description:
|
||||
TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip
|
||||
variants. It is designed to be clicked on different carrier boards.
|
||||
items:
|
||||
- enum:
|
||||
- tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx
|
||||
- const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM
|
||||
- const: fsl,imx8mq
|
||||
|
||||
- description: Zodiac Inflight Innovations Ultra Boards
|
||||
items:
|
||||
- enum:
|
||||
@ -834,6 +906,12 @@ properties:
|
||||
- const: toradex,colibri-imx8x
|
||||
- const: fsl,imx8qxp
|
||||
|
||||
- description: i.MX8ULP based Boards
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx8ulp-evk # i.MX8ULP EVK Board
|
||||
- const: fsl,imx8ulp
|
||||
|
||||
- description:
|
||||
Freescale Vybrid Platform Device Tree Bindings
|
||||
|
||||
|
||||
@ -77,6 +77,14 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt7629-rfb
|
||||
- const: mediatek,mt7629
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7986a-rfb
|
||||
- const: mediatek,mt7986a
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt7986b-rfb
|
||||
- const: mediatek,mt7986b
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt8127-moose
|
||||
@ -134,6 +142,10 @@ properties:
|
||||
- google,krane-sku176
|
||||
- const: google,krane
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Cozmo (Acer Chromebook 314)
|
||||
items:
|
||||
- const: google,cozmo
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Damu (ASUS Chromebook Flip CM3)
|
||||
items:
|
||||
- const: google,damu
|
||||
@ -143,7 +155,9 @@ properties:
|
||||
- enum:
|
||||
- google,fennel-sku0
|
||||
- google,fennel-sku1
|
||||
- google,fennel-sku2
|
||||
- google,fennel-sku6
|
||||
- google,fennel-sku7
|
||||
- const: google,fennel
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
|
||||
@ -159,6 +173,12 @@ properties:
|
||||
- const: google,kakadu-rev2
|
||||
- const: google,kakadu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
|
||||
items:
|
||||
- const: google,kakadu-rev3-sku22
|
||||
- const: google,kakadu-rev2-sku22
|
||||
- const: google,kakadu
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Kappa (HP Chromebook 11a)
|
||||
items:
|
||||
- const: google,kappa
|
||||
|
||||
@ -24,6 +24,7 @@ properties:
|
||||
- qcom,sc7180-llcc
|
||||
- qcom,sc7280-llcc
|
||||
- qcom,sdm845-llcc
|
||||
- qcom,sm6350-llcc
|
||||
- qcom,sm8150-llcc
|
||||
- qcom,sm8250-llcc
|
||||
|
||||
@ -44,7 +45,6 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -48,8 +48,10 @@ description: |
|
||||
sdx65
|
||||
sm7225
|
||||
sm8150
|
||||
sdx65
|
||||
sm8250
|
||||
sm8350
|
||||
sm8450
|
||||
|
||||
The 'board' element must be one of the following strings:
|
||||
|
||||
@ -201,8 +203,10 @@ properties:
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sc7280-crd
|
||||
- qcom,sc7280-idp
|
||||
- qcom,sc7280-idp2
|
||||
- google,hoglin
|
||||
- google,piglin
|
||||
- google,senor
|
||||
- const: qcom,sc7280
|
||||
@ -224,6 +228,11 @@ properties:
|
||||
- qcom,sdx65-mtp
|
||||
- const: qcom,sdx65
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sdx65-mtp
|
||||
- const: qcom,sdx65
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq6018-cp01
|
||||
@ -257,6 +266,11 @@ properties:
|
||||
- qcom,sm8350-mtp
|
||||
- const: qcom,sm8350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8450-qrd
|
||||
- const: qcom,sm8450
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
@ -315,6 +315,18 @@ properties:
|
||||
- const: renesas,falcon-cpu
|
||||
- const: renesas,r8a779a0
|
||||
|
||||
- description: R-Car S4-8 (R8A779F0)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S)
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S)
|
||||
- const: renesas,spider-cpu
|
||||
- const: renesas,r8a779f0
|
||||
|
||||
- description: R-Car H3e (R8A779M0)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -199,6 +199,18 @@ properties:
|
||||
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
|
||||
- const: samsung,exynos7
|
||||
|
||||
- description: Exynos7885 based boards
|
||||
items:
|
||||
- enum:
|
||||
- samsung,jackpotlte # Samsung Galaxy A8 (2018)
|
||||
- const: samsung,exynos7885
|
||||
|
||||
- description: Exynos850 based boards
|
||||
items:
|
||||
- enum:
|
||||
- winlink,e850-96 # WinLink E850-96
|
||||
- const: samsung,exynos850
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -77,6 +77,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
|
||||
- engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
|
||||
- engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
|
||||
- const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
|
||||
- const: st,stm32mp157
|
||||
|
||||
@ -808,6 +808,11 @@ properties:
|
||||
- const: oranth,tanix-tx6
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: Tanix TX6 mini
|
||||
items:
|
||||
- const: oranth,tanix-tx6-mini
|
||||
- const: allwinner,sun50i-h6
|
||||
|
||||
- description: TBS A711 Tablet
|
||||
items:
|
||||
- const: tbs-biometrics,a711
|
||||
|
||||
@ -32,12 +32,38 @@ properties:
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun8i-r40-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
- allwinner,sun50i-h5-mbus
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
items:
|
||||
- description: MBUS interconnect/bandwidth limit/PMU registers
|
||||
- description: DRAM controller/PHY registers
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mbus
|
||||
- const: dram
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: MBUS interconnect module clock
|
||||
- description: DRAM controller/PHY module clock
|
||||
- description: Register bus clock, shared by MBUS and DRAM
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mbus
|
||||
- const: dram
|
||||
- const: bus
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description:
|
||||
MBUS PMU activity interrupt.
|
||||
|
||||
dma-ranges:
|
||||
description:
|
||||
@ -54,13 +80,55 @@ required:
|
||||
- clocks
|
||||
- dma-ranges
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun8i-h3-mbus
|
||||
- allwinner,sun50i-a64-mbus
|
||||
- allwinner,sun50i-h5-mbus
|
||||
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
|
||||
clocks:
|
||||
minItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 3
|
||||
|
||||
required:
|
||||
- reg-names
|
||||
- clock-names
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/sun5i-ccu.h>
|
||||
#include <dt-bindings/clock/sun50i-a64-ccu.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mbus: dram-controller@1c01000 {
|
||||
dram-controller@1c01000 {
|
||||
compatible = "allwinner,sun5i-a13-mbus";
|
||||
reg = <0x01c01000 0x1000>;
|
||||
clocks = <&ccu CLK_MBUS>;
|
||||
@ -70,4 +138,21 @@ examples:
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
- |
|
||||
dram-controller@1c62000 {
|
||||
compatible = "allwinner,sun50i-a64-mbus";
|
||||
reg = <0x01c62000 0x1000>,
|
||||
<0x01c63000 0x1000>;
|
||||
reg-names = "mbus", "dram";
|
||||
clocks = <&ccu CLK_MBUS>,
|
||||
<&ccu CLK_DRAM>,
|
||||
<&ccu CLK_BUS_DRAM>;
|
||||
clock-names = "mbus", "dram", "bus";
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
|
||||
#interconnect-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
@ -36,6 +36,9 @@ properties:
|
||||
- toradex,colibri_t20-iris
|
||||
- const: toradex,colibri_t20
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- const: asus,tf101
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- const: acer,picasso
|
||||
- const: nvidia,tegra20
|
||||
@ -49,6 +52,18 @@ properties:
|
||||
- nvidia,cardhu-a04
|
||||
- const: nvidia,cardhu
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf201
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300t
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf300tg
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tf700t
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: toradex,apalis_t30-eval
|
||||
- const: toradex,apalis_t30
|
||||
@ -74,8 +89,12 @@ properties:
|
||||
- items:
|
||||
- const: ouya,ouya
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: pegatron,chagall
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- asus,tf701t
|
||||
- nvidia,dalmore
|
||||
- nvidia,roth
|
||||
- nvidia,tn7
|
||||
@ -108,14 +127,17 @@ properties:
|
||||
- nvidia,p2571
|
||||
- nvidia,p2894-0050-a08
|
||||
- const: nvidia,tegra210
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2771-0000
|
||||
- nvidia,p3509-0000+p3636-0001
|
||||
- description: Jetson TX2 Developer Kit
|
||||
items:
|
||||
- const: nvidia,p2771-0000
|
||||
- const: nvidia,tegra186
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,p2972-0000
|
||||
- description: Jetson TX2 NX Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3509-0000+p3636-0001
|
||||
- const: nvidia,tegra186
|
||||
- description: Jetson AGX Xavier Developer Kit
|
||||
items:
|
||||
- const: nvidia,p2972-0000
|
||||
- const: nvidia,tegra194
|
||||
- description: Jetson Xavier NX
|
||||
items:
|
||||
@ -134,8 +156,16 @@ properties:
|
||||
- const: nvidia,p3509-0000+p3668-0001
|
||||
- const: nvidia,tegra194
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-vdk
|
||||
- const: nvidia,tegra234-vdk
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin
|
||||
items:
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
- description: Jetson AGX Orin Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3737-0000+p3701-0000
|
||||
- const: nvidia,p3701-0000
|
||||
- const: nvidia,tegra234
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@ -1,133 +0,0 @@
|
||||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain one of the following:
|
||||
- "nvidia,tegra186-pmc": for Tegra186
|
||||
- "nvidia,tegra194-pmc": for Tegra194
|
||||
- "nvidia,tegra234-pmc": for Tegra234
|
||||
- reg: Must contain an (offset, length) pair of the register set for each
|
||||
entry in reg-names.
|
||||
- reg-names: Must include the following entries:
|
||||
- "pmc"
|
||||
- "wake"
|
||||
- "aotag"
|
||||
- "scratch"
|
||||
- "misc" (Only for Tegra194 and later)
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
|
||||
- interrupt-controller: Identifies the node as an interrupt controller.
|
||||
- #interrupt-cells: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 2.
|
||||
|
||||
Example:
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pmc@c3600000 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0 0x0c360000 0 0x10000>,
|
||||
<0 0x0c370000 0 0x10000>,
|
||||
<0 0x0c380000 0 0x10000>,
|
||||
<0 0x0c390000 0 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
};
|
||||
|
||||
Board DTS:
|
||||
|
||||
pmc@c360000 {
|
||||
nvidia,invert-interrupt;
|
||||
};
|
||||
|
||||
== Pad Control ==
|
||||
|
||||
On Tegra SoCs a pad is a set of pins which are configured as a group.
|
||||
The pin grouping is a fixed attribute of the hardware. The PMC can be
|
||||
used to set pad power state and signaling voltage. A pad can be either
|
||||
in active or power down mode. The support for power state and signaling
|
||||
voltage configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
Pad configurations are described with pin configuration nodes which
|
||||
are placed under the pmc node and they are referred to by the pinctrl
|
||||
client properties. For more information see
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
|
||||
|
||||
The following pads are present on Tegra186:
|
||||
csia csib dsi mipi-bias
|
||||
pex-clk-bias pex-clk3 pex-clk2 pex-clk1
|
||||
usb0 usb1 usb2 usb-bias
|
||||
uart audio hsic dbg
|
||||
hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
|
||||
sdmmc4 cam dsib dsic
|
||||
dsid csic csid csie
|
||||
dsif spi ufs dmic-hv
|
||||
edp sdmmc1-hv sdmmc3-hv conn
|
||||
audio-hv ao-hv
|
||||
|
||||
Required pin configuration properties:
|
||||
- pins: A list of strings, each of which contains the name of a pad
|
||||
to be configured.
|
||||
|
||||
Optional pin configuration properties:
|
||||
- low-power-enable: Configure the pad into power down mode
|
||||
- low-power-disable: Configure the pad into active mode
|
||||
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
|
||||
The values are defined in
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
|
||||
|
||||
Note: The power state can be configured on all of the above pads except
|
||||
for ao-hv. Following pads have software configurable signaling
|
||||
voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
|
||||
ao-hv.
|
||||
|
||||
Pad configuration state example:
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0 0x0c360000 0 0x10000>,
|
||||
<0 0x0c370000 0 0x10000>,
|
||||
<0 0x0c380000 0 0x10000>,
|
||||
<0 0x0c390000 0 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
|
||||
...
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
|
||||
hdmi_off: hdmi-off {
|
||||
pins = "hdmi";
|
||||
low-power-enable;
|
||||
}
|
||||
|
||||
hdmi_on: hdmi-on {
|
||||
pins = "hdmi";
|
||||
low-power-disable;
|
||||
}
|
||||
};
|
||||
|
||||
Pinctrl client example:
|
||||
sdmmc1: sdhci@3400000 {
|
||||
...
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
|
||||
...
|
||||
|
||||
sor0: sor@15540000 {
|
||||
...
|
||||
pinctrl-0 = <&hdmi_off>;
|
||||
pinctrl-1 = <&hdmi_on>;
|
||||
pinctrl-names = "hdmi-on", "hdmi-off";
|
||||
};
|
||||
@ -0,0 +1,198 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-pmc
|
||||
- nvidia,tegra194-pmc
|
||||
- nvidia,tegra234-pmc
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
maxItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: pmc
|
||||
- const: wake
|
||||
- const: aotag
|
||||
- const: scratch
|
||||
- const: misc
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
description: Specifies the number of cells needed to encode an
|
||||
interrupt source. The value must be 2.
|
||||
const: 2
|
||||
|
||||
nvidia,invert-interrupt:
|
||||
description: If present, inverts the PMU interrupt signal.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra186-pmc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
|
||||
reg-names:
|
||||
minItems: 5
|
||||
|
||||
patternProperties:
|
||||
"^[a-z0-9]+-[a-z0-9]+$":
|
||||
if:
|
||||
type: object
|
||||
then:
|
||||
description: |
|
||||
These are pad configuration nodes. On Tegra SoCs a pad is a set of
|
||||
pins which are configured as a group. The pin grouping is a fixed
|
||||
attribute of the hardware. The PMC can be used to set pad power
|
||||
state and signaling voltage. A pad can be either in active or
|
||||
power down mode. The support for power state and signaling voltage
|
||||
configuration varies depending on the pad in question. 3.3 V and
|
||||
1.8 V signaling voltages are supported on pins where software
|
||||
controllable signaling voltage switching is available.
|
||||
|
||||
Pad configurations are described with pin configuration nodes
|
||||
which are placed under the pmc node and they are referred to by
|
||||
the pinctrl client properties. For more information see
|
||||
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
The following pads are present on Tegra186:
|
||||
|
||||
csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
||||
pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
|
||||
hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
|
||||
dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
|
||||
sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
|
||||
|
||||
The following pads are present on Tegra194:
|
||||
|
||||
csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
|
||||
pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
|
||||
pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
|
||||
soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
|
||||
hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
|
||||
pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
|
||||
spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
|
||||
audio-hv, ao-hv
|
||||
|
||||
properties:
|
||||
pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: Must contain the name of the pad(s) to be
|
||||
configured.
|
||||
|
||||
low-power-enable:
|
||||
description: Configure the pad into power down mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
low-power-disable:
|
||||
description: Configure the pad into active mode.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
power-source:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
|
||||
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
|
||||
voltages.
|
||||
|
||||
The values are defined in
|
||||
|
||||
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
|
||||
|
||||
The power state can be configured on all of the above pads
|
||||
except for ao-hv. Following pads have software configurable
|
||||
signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
|
||||
audio-hv, ao-hv.
|
||||
|
||||
phandle: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
dependencies:
|
||||
interrupt-controller: ['#interrupt-cells']
|
||||
"#interrupt-cells":
|
||||
required:
|
||||
- interrupt-controller
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
pmc@c3600000 {
|
||||
compatible = "nvidia,tegra186-pmc";
|
||||
reg = <0x0c360000 0x10000>,
|
||||
<0x0c370000 0x10000>,
|
||||
<0x0c380000 0x10000>,
|
||||
<0x0c390000 0x10000>;
|
||||
reg-names = "pmc", "wake", "aotag", "scratch";
|
||||
nvidia,invert-interrupt;
|
||||
|
||||
sdmmc1_3v3: sdmmc1-3v3 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
|
||||
};
|
||||
|
||||
sdmmc1_1v8: sdmmc1-1v8 {
|
||||
pins = "sdmmc1-hv";
|
||||
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1: mmc@3400000 {
|
||||
compatible = "nvidia,tegra186-sdhci";
|
||||
reg = <0x03400000 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
|
||||
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
|
||||
reset-names = "sdhci";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_SDMMC1>;
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
};
|
||||
@ -53,6 +53,12 @@ properties:
|
||||
- ti,am642-sk
|
||||
- const: ti,am642
|
||||
|
||||
- description: K3 J721s2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- ti,j721s2-evm
|
||||
- const: ti,j721s2
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
...
|
||||
|
||||
68
Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
Normal file
68
Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
Normal file
@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Shared Peripherals Bus Interface
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
|
||||
description: |
|
||||
A simple bus enabling access to shared peripherals.
|
||||
|
||||
The "spba-bus" follows the "simple-bus" set of properties, as
|
||||
specified in the Devicetree Specification. It is an extension of
|
||||
"simple-bus" because the SDMA controller uses this compatible flag to
|
||||
determine which peripherals are available to it and the range over which
|
||||
the SDMA can access. There are no special clocks for the bus, because
|
||||
the SDMA controller itself has its interrupt and clock assignments.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,spba-bus
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^spba-bus(@[0-9a-f]+)?$"
|
||||
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,spba-bus
|
||||
- const: simple-bus
|
||||
|
||||
'#address-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#size-cells':
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- reg
|
||||
- ranges
|
||||
|
||||
additionalProperties:
|
||||
type: object
|
||||
|
||||
examples:
|
||||
- |
|
||||
spba-bus@30000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000000 0x100000>;
|
||||
ranges;
|
||||
};
|
||||
@ -48,6 +48,11 @@ Optional properties:
|
||||
devices, the presence of this property indicates that
|
||||
the weim bus should operate in Burst Clock Mode.
|
||||
|
||||
- fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
|
||||
Without this option Burst Clock will output clock
|
||||
only when necessary. This takes effect only if
|
||||
"fsl,burst-clk-enable" is set.
|
||||
|
||||
Timing property for child nodes. It is mandatory, not optional.
|
||||
|
||||
- fsl,weim-cs-timing: The timing array, contains timing values for the
|
||||
|
||||
@ -42,6 +42,36 @@ properties:
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^(sclk)|(pll-[cem])$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra20-sclk
|
||||
- nvidia,tegra30-sclk
|
||||
- nvidia,tegra30-pllc
|
||||
- nvidia,tegra30-plle
|
||||
- nvidia,tegra30-pllm
|
||||
|
||||
operating-points-v2: true
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: node's clock
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description: phandle to the core SoC power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- operating-points-v2
|
||||
- clocks
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -59,6 +89,13 @@ examples:
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
sclk {
|
||||
compatible = "nvidia,tegra20-sclk";
|
||||
operating-points-v2 = <&opp_table>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
};
|
||||
|
||||
usb-controller@c5004000 {
|
||||
|
||||
80
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
Normal file
80
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
Normal file
@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
|
||||
|
||||
maintainers:
|
||||
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SDX65
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sdx65.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sdx65
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE Pipe clock source
|
||||
- description: USB3 phy wrapper pipe clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
minItems: 5
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
- const: pcie_pipe_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
minItems: 5
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdx65";
|
||||
reg = <0x100000 0x1f7400>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
|
||||
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
|
||||
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
85
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
Normal file
85
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
Normal file
@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8450
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8450
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8450.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8450
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Phy Auxillary clock source (Optional clock)
|
||||
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS Phy Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS Phy Tx symbol 0 clock source (Optional clock)
|
||||
- description: USB3 Phy wrapper pipe clock source (Optional clock)
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk # Optional clock
|
||||
- const: pcie_1_pipe_clk # Optional clock
|
||||
- const: pcie_1_phy_aux_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_phy_tx_symbol_0_clk # Optional clock
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8450";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7100 Clock Generator
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert@linux-m68k.org>
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7100-clkgen
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Main clock source (25 MHz)
|
||||
- description: Application-specific clock source (12-27 MHz)
|
||||
- description: RMII reference clock (50 MHz)
|
||||
- description: RGMII RX clock (125 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: osc_sys
|
||||
- const: osc_aud
|
||||
- const: gmac_rmii_ref
|
||||
- const: gmac_gr_mii_rxclk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
description:
|
||||
See <dt-bindings/clock/starfive-jh7100.h> for valid indices.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@11800000 {
|
||||
compatible = "starfive,jh7100-clkgen";
|
||||
reg = <0x11800000 0x10000>;
|
||||
clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
|
||||
clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@ -44,6 +44,16 @@ properties:
|
||||
- const: ahb
|
||||
- const: mod
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: RX DMA Channel
|
||||
- description: TX DMA Channel
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
|
||||
@ -19,6 +19,19 @@ Required properties:
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- host1x
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
For each opp entry in 'operating-points-v2' table of host1x and its modules:
|
||||
- opp-supported-hw: One bitfield indicating:
|
||||
On Tegra20: SoC process ID mask
|
||||
On Tegra30+: SoC speedo ID mask
|
||||
|
||||
A bitwise AND is performed against the value and if any bit
|
||||
matches, the OPP gets enabled.
|
||||
|
||||
Each host1x client module having to perform DMA through the Memory Controller
|
||||
should have the interconnect endpoints set to the Memory Client and External
|
||||
@ -45,6 +58,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to MPE power domain.
|
||||
|
||||
- vi: video input
|
||||
|
||||
@ -128,6 +143,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to VENC power domain.
|
||||
|
||||
- epp: encoder pre-processor
|
||||
|
||||
@ -147,6 +164,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- isp: image signal processor
|
||||
|
||||
@ -166,6 +185,7 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- power-domains: Phandle to VENC or core power domain.
|
||||
|
||||
- gr2d: 2D graphics engine
|
||||
|
||||
@ -179,12 +199,15 @@ of the following host1x client modules:
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- 2d
|
||||
- mc
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR2D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to HEG or core power domain.
|
||||
|
||||
- gr3d: 3D graphics engine
|
||||
|
||||
@ -203,12 +226,16 @@ of the following host1x client modules:
|
||||
- reset-names: Must include the following entries:
|
||||
- 3d
|
||||
- 3d2 (Only required on SoCs with two 3D clocks)
|
||||
- mc
|
||||
- mc2 (Only required on SoCs with two 3D clocks)
|
||||
|
||||
Optional properties:
|
||||
- interconnects: Must contain entry for the GR3D memory clients.
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandles to 3D or core power domain.
|
||||
|
||||
- dc: display controller
|
||||
|
||||
@ -241,6 +268,8 @@ of the following host1x client modules:
|
||||
- interconnect-names: Must include name of the interconnect path for each
|
||||
interconnect entry. Consult TRM documentation for information about
|
||||
available memory clients, see MEMORY CONTROLLER section.
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- hdmi: High Definition Multimedia Interface
|
||||
|
||||
@ -267,6 +296,7 @@ of the following host1x client modules:
|
||||
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
|
||||
- nvidia,edid: supplies a binary EDID blob
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- tvo: TV encoder output
|
||||
|
||||
@ -277,6 +307,10 @@ of the following host1x client modules:
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Optional properties:
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
- power-domains: Phandle to core power domain.
|
||||
|
||||
- dsi: display serial interface
|
||||
|
||||
Required properties:
|
||||
@ -305,6 +339,7 @@ of the following host1x client modules:
|
||||
- nvidia,panel: phandle of a display panel
|
||||
- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
|
||||
up with in order to support up to 8 data lanes
|
||||
- operating-points-v2: See ../bindings/opp/opp.txt for details.
|
||||
|
||||
- sor: serial output resource
|
||||
|
||||
@ -408,6 +443,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
|
||||
resets = <&tegra_car 28>;
|
||||
reset-names = "host1x";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -421,6 +458,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_MPE>;
|
||||
resets = <&tegra_car 60>;
|
||||
reset-names = "mpe";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
vi@54080000 {
|
||||
@ -429,6 +468,7 @@ Example:
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_VI>;
|
||||
power-domains = <&pd_venc>;
|
||||
@ -510,6 +550,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_EPP>;
|
||||
resets = <&tegra_car 19>;
|
||||
reset-names = "epp";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
isp {
|
||||
@ -528,6 +570,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
|
||||
resets = <&tegra_car 21>;
|
||||
reset-names = "2d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
@ -536,6 +580,8 @@ Example:
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>;
|
||||
reset-names = "3d";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
|
||||
dc@54200000 {
|
||||
@ -547,6 +593,8 @@ Example:
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 27>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0B &emc>,
|
||||
@ -571,6 +619,8 @@ Example:
|
||||
clock-names = "dc", "parent";
|
||||
resets = <&tegra_car 26>;
|
||||
reset-names = "dc";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
|
||||
interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
|
||||
<&mc TEGRA20_MC_DISPLAY0BB &emc>,
|
||||
@ -596,6 +646,7 @@ Example:
|
||||
resets = <&tegra_car 51>;
|
||||
reset-names = "hdmi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
tvo {
|
||||
@ -604,6 +655,7 @@ Example:
|
||||
interrupts = <0 76 0x04>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_TVO>;
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
|
||||
dsi {
|
||||
@ -615,6 +667,7 @@ Example:
|
||||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
status = "disabled";
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -1,107 +0,0 @@
|
||||
NVIDIA Tegra Boot and Power Management Processor (BPMP)
|
||||
|
||||
The BPMP is a specific processor in Tegra chip, which is designed for
|
||||
booting process handling and offloading the power management, clock
|
||||
management, and reset control tasks from the CPU. The binding document
|
||||
defines the resources that would be used by the BPMP firmware driver,
|
||||
which can create the interprocessor communication (IPC) between the CPU
|
||||
and BPMP.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
- "nvidia,tegra186-bpmp"
|
||||
- mboxes : The phandle of mailbox controller and the mailbox specifier.
|
||||
- shmem : List of the phandle of the TX and RX shared memory area that
|
||||
the IPC between CPU and BPMP is based on.
|
||||
- #clock-cells : Should be 1.
|
||||
- #power-domain-cells : Should be 1.
|
||||
- #reset-cells : Should be 1.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details of
|
||||
the mailbox subsystem, and the specifiers implemented by the relevant
|
||||
provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.txt
|
||||
|
||||
This node is a clock, power domain, and reset provider. See the following
|
||||
files for general documentation of those features, and the specifiers
|
||||
implemented by this node:
|
||||
|
||||
- .../clock/clock-bindings.txt
|
||||
- <dt-bindings/clock/tegra186-clock.h>
|
||||
- ../power/power-domain.yaml
|
||||
- <dt-bindings/power/tegra186-powergate.h>
|
||||
- .../reset/reset.txt
|
||||
- <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
The BPMP implements some services which must be represented by separate nodes.
|
||||
For example, it can provide access to certain I2C controllers, and the I2C
|
||||
bindings represent each I2C controller as a device tree node. Such nodes should
|
||||
be nested directly inside the main BPMP node.
|
||||
|
||||
Software can determine whether a child node of the BPMP node represents a device
|
||||
by checking for a compatible property. Any node with a compatible property
|
||||
represents a device that can be instantiated. Nodes without a compatible
|
||||
property may be used to provide configuration information regarding the BPMP
|
||||
itself, although no such configuration nodes are currently defined by this
|
||||
binding.
|
||||
|
||||
The BPMP firmware defines no single global name-/numbering-space for such
|
||||
services. Put another way, the numbering scheme for I2C buses is distinct from
|
||||
the numbering scheme for any other service the BPMP may provide (e.g. a future
|
||||
hypothetical SPI bus service). As such, child device nodes will have no reg
|
||||
property, and the BPMP node will have no #address-cells or #size-cells property.
|
||||
|
||||
The shared memory bindings for BPMP
|
||||
-----------------------------------
|
||||
|
||||
The shared memory area for the IPC TX and RX between CPU and BPMP are
|
||||
predefined and work on top of sysram, which is an SRAM inside the chip.
|
||||
|
||||
See ".../sram/sram.txt" for the bindings.
|
||||
|
||||
Example:
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
...
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
sysram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x0 0x30000000 0x0 0x50000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
|
||||
|
||||
cpu_bpmp_tx: shmem@4e000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4e000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-tx";
|
||||
pool;
|
||||
};
|
||||
|
||||
cpu_bpmp_rx: shmem@4f000 {
|
||||
compatible = "nvidia,tegra186-bpmp-shmem";
|
||||
reg = <0x0 0x4f000 0x0 0x1000>;
|
||||
label = "cpu-bpmp-rx";
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
|
||||
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
i2c {
|
||||
compatible = "...";
|
||||
...
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,186 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The BPMP is a specific processor in Tegra chip, which is designed for
|
||||
booting process handling and offloading the power management, clock
|
||||
management, and reset control tasks from the CPU. The binding document
|
||||
defines the resources that would be used by the BPMP firmware driver,
|
||||
which can create the interprocessor communication (IPC) between the
|
||||
CPU and BPMP.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details
|
||||
of the mailbox subsystem, and the specifiers implemented by the
|
||||
relevant provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.yaml
|
||||
|
||||
This node is a clock, power domain, and reset provider. See the
|
||||
following files for general documentation of those features, and the
|
||||
specifiers implemented by this node:
|
||||
|
||||
- .../clock/clock-bindings.txt
|
||||
- <dt-bindings/clock/tegra186-clock.h>
|
||||
- ../power/power-domain.yaml
|
||||
- <dt-bindings/power/tegra186-powergate.h>
|
||||
- .../reset/reset.txt
|
||||
- <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
The BPMP implements some services which must be represented by
|
||||
separate nodes. For example, it can provide access to certain I2C
|
||||
controllers, and the I2C bindings represent each I2C controller as a
|
||||
device tree node. Such nodes should be nested directly inside the main
|
||||
BPMP node.
|
||||
|
||||
Software can determine whether a child node of the BPMP node
|
||||
represents a device by checking for a compatible property. Any node
|
||||
with a compatible property represents a device that can be
|
||||
instantiated. Nodes without a compatible property may be used to
|
||||
provide configuration information regarding the BPMP itself, although
|
||||
no such configuration nodes are currently defined by this binding.
|
||||
|
||||
The BPMP firmware defines no single global name-/numbering-space for
|
||||
such services. Put another way, the numbering scheme for I2C buses is
|
||||
distinct from the numbering scheme for any other service the BPMP may
|
||||
provide (e.g. a future hypothetical SPI bus service). As such, child
|
||||
device nodes will have no reg property, and the BPMP node will have no
|
||||
"#address-cells" or "#size-cells" property.
|
||||
|
||||
The shared memory area for the IPC TX and RX between CPU and BPMP are
|
||||
predefined and work on top of sysram, which is an SRAM inside the
|
||||
chip. See ".../sram/sram.yaml" for the bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra194-bpmp
|
||||
- nvidia,tegra234-bpmp
|
||||
- const: nvidia,tegra186-bpmp
|
||||
- const: nvidia,tegra186-bpmp
|
||||
|
||||
mboxes:
|
||||
description: A phandle and channel specifier for the mailbox used to
|
||||
communicate with the BPMP.
|
||||
maxItems: 1
|
||||
|
||||
shmem:
|
||||
description: List of the phandle to the TX and RX shared memory area
|
||||
that the IPC between CPU and BPMP is based on.
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
- description: DMA read client
|
||||
- description: DMA write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: read
|
||||
- const: write
|
||||
- const: dma-mem # dma-read
|
||||
- const: dma-write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
i2c:
|
||||
type: object
|
||||
|
||||
thermal:
|
||||
type: object
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
- shmem
|
||||
- "#clock-cells"
|
||||
- "#power-domain-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x03c00000 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
sram@30000000 {
|
||||
compatible = "nvidia,tegra186-sysram", "mmio-sram";
|
||||
reg = <0x30000000 0x50000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x30000000 0x50000>;
|
||||
|
||||
cpu_bpmp_tx: sram@4e000 {
|
||||
reg = <0x4e000 0x1000>;
|
||||
label = "cpu-bpmp-tx";
|
||||
pool;
|
||||
};
|
||||
|
||||
cpu_bpmp_rx: sram@4f000 {
|
||||
reg = <0x4f000 0x1000>;
|
||||
label = "cpu-bpmp-rx";
|
||||
pool;
|
||||
};
|
||||
};
|
||||
|
||||
bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
|
||||
interconnect-names = "read", "write", "dma-mem", "dma-write";
|
||||
iommus = <&smmu TEGRA186_SID_BPMP>;
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
|
||||
TEGRA_HSP_DB_MASTER_BPMP>;
|
||||
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
||||
i2c {
|
||||
compatible = "nvidia,tegra186-bpmp-i2c";
|
||||
nvidia,bpmp-bus-id = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
thermal {
|
||||
compatible = "nvidia,tegra186-bpmp-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -26,9 +26,11 @@ Required properties:
|
||||
* "qcom,scm-sc7280"
|
||||
* "qcom,scm-sdm845"
|
||||
* "qcom,scm-sdx55"
|
||||
* "qcom,scm-sm6350"
|
||||
* "qcom,scm-sm8150"
|
||||
* "qcom,scm-sm8250"
|
||||
* "qcom,scm-sm8350"
|
||||
* "qcom,scm-sm8450"
|
||||
and:
|
||||
* "qcom,scm"
|
||||
- clocks: Specifies clocks needed by the SCM interface, if any:
|
||||
|
||||
@ -1,42 +0,0 @@
|
||||
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.
|
||||
|
||||
Required properties:
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
|
||||
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
|
||||
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
|
||||
For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
|
||||
For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
|
||||
"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
|
||||
For Tegra234 must contain "nvidia,tegra234-efuse".
|
||||
Details:
|
||||
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
|
||||
due to a hardware bug. Tegra20 also lacks certain information which is
|
||||
available in later generations such as fab code, lot code, wafer id,..
|
||||
nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse:
|
||||
The differences between these SoCs are the size of the efuse array,
|
||||
the location of the spare (OEM programmable) bits and the location of
|
||||
the speedo data.
|
||||
- reg: Should contain 1 entry: the entry gives the physical address and length
|
||||
of the fuse registers.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- fuse
|
||||
|
||||
Example:
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000f800 0x400>,
|
||||
<0x70000000 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
|
||||
|
||||
@ -0,0 +1,89 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/fuse/nvidia,tegra20-fuse.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra FUSE block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-efuse
|
||||
- nvidia,tegra30-efuse
|
||||
- nvidia,tegra114-efuse
|
||||
- nvidia,tegra124-efuse
|
||||
- nvidia,tegra210-efuse
|
||||
- nvidia,tegra186-efuse
|
||||
- nvidia,tegra194-efuse
|
||||
- nvidia,tegra234-efuse
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-efuse
|
||||
- const: nvidia,tegra124-efuse
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fuse
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: fuse
|
||||
|
||||
operating-points-v2:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra20-efuse
|
||||
- nvidia,tegra30-efuse
|
||||
- nvidia,tegra114-efuse
|
||||
- nvidia,tegra124-efuse
|
||||
- nvidia,tegra132-efuse
|
||||
- nvidia,tegra210-efuse
|
||||
then:
|
||||
required:
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
fuse@7000f800 {
|
||||
compatible = "nvidia,tegra20-efuse";
|
||||
reg = <0x7000f800 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_FUSE>;
|
||||
clock-names = "fuse";
|
||||
resets = <&tegra_car 39>;
|
||||
reset-names = "fuse";
|
||||
};
|
||||
@ -0,0 +1,135 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVENC
|
||||
|
||||
description: |
|
||||
NVENC is the hardware video encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvenc@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
- nvidia,tegra194-nvenc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvenc
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
interconnect-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
nvidia,host1x-class:
|
||||
description: |
|
||||
Host1x class of the engine, used to specify the targeted engine
|
||||
when programming the engine through Host1x channels or when
|
||||
configuring engine-specific behavior in Host1x.
|
||||
default: 0x21
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvenc
|
||||
- nvidia,tegra186-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-nvenc
|
||||
then:
|
||||
properties:
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA read 2 memory client
|
||||
- description: DMA write memory client
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: read-1
|
||||
- const: write
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvenc@154c0000 {
|
||||
compatible = "nvidia,tegra186-nvenc";
|
||||
reg = <0x154c0000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVENC>;
|
||||
clock-names = "nvenc";
|
||||
resets = <&bpmp TEGRA186_RESET_NVENC>;
|
||||
reset-names = "nvenc";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVENC>;
|
||||
};
|
||||
@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra NVJPG
|
||||
|
||||
description: |
|
||||
NVJPG is the hardware JPEG decoder and encoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically programmed
|
||||
through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvjpg@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra210-nvjpg
|
||||
- nvidia,tegra186-nvjpg
|
||||
- nvidia,tegra194-nvjpg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvjpg
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
nvjpg@15380000 {
|
||||
compatible = "nvidia,tegra186-nvjpg";
|
||||
reg = <0x15380000 0x40000>;
|
||||
clocks = <&bpmp TEGRA186_CLK_NVJPG>;
|
||||
clock-names = "nvjpg";
|
||||
resets = <&bpmp TEGRA186_RESET_NVJPG>;
|
||||
reset-names = "nvjpg";
|
||||
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_NVJPG>;
|
||||
};
|
||||
@ -21,7 +21,9 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: apple,t8103-i2c
|
||||
- enum:
|
||||
- apple,t8103-i2c
|
||||
- apple,t6000-i2c
|
||||
- const: apple,i2c
|
||||
|
||||
reg:
|
||||
@ -40,6 +42,9 @@ properties:
|
||||
used. This frequency is generated by dividing the reference clock.
|
||||
Allowed values are between ref_clk/(16*4) and ref_clk/(16*255).
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -65,6 +65,9 @@ properties:
|
||||
Specifies base physical address and size of the AIC registers.
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#interrupt-cells'
|
||||
|
||||
@ -45,6 +45,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-plic
|
||||
- starfive,jh7100-plic
|
||||
- canaan,k210-plic
|
||||
- const: sifive,plic-1.0.0
|
||||
|
||||
|
||||
@ -41,6 +41,9 @@ properties:
|
||||
Has to be one. The single cell describes the stream id emitted by
|
||||
a master to the IOMMU.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -11,6 +11,7 @@ Required properties:
|
||||
"aspeed,ast2500-ibt-bmc"
|
||||
"aspeed,ast2600-ibt-bmc"
|
||||
- reg: physical address and size of the registers
|
||||
- clocks: clock for the device
|
||||
|
||||
Optional properties:
|
||||
|
||||
@ -23,4 +24,5 @@ Example:
|
||||
compatible = "aspeed,ast2400-ibt-bmc";
|
||||
reg = <0x1e789140 0x18>;
|
||||
interrupts = <8>;
|
||||
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
|
||||
};
|
||||
|
||||
@ -56,6 +56,9 @@ properties:
|
||||
"#mbox-cells":
|
||||
const: 0
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@ -1,72 +0,0 @@
|
||||
NVIDIA Tegra Hardware Synchronization Primitives (HSP)
|
||||
|
||||
The HSP modules are used for the processors to share resources and communicate
|
||||
together. It provides a set of hardware synchronization primitives for
|
||||
interprocessor communication. So the interprocessor communication (IPC)
|
||||
protocols can use hardware synchronization primitives, when operating between
|
||||
two processors not in an SMP relationship.
|
||||
|
||||
The features that HSP supported are shared mailboxes, shared semaphores,
|
||||
arbitrated semaphores and doorbells.
|
||||
|
||||
Required properties:
|
||||
- name : Should be hsp
|
||||
- compatible
|
||||
Array of strings.
|
||||
one of:
|
||||
- "nvidia,tegra186-hsp"
|
||||
- "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
|
||||
- reg : Offset and length of the register set for the device.
|
||||
- interrupt-names
|
||||
Array of strings.
|
||||
Contains a list of names for the interrupts described by the interrupt
|
||||
property. May contain the following entries, in any order:
|
||||
- "doorbell"
|
||||
- "sharedN", where 'N' is a number from zero up to the number of
|
||||
external interrupts supported by the HSP instance minus one.
|
||||
Users of this binding MUST look up entries in the interrupt property
|
||||
by name, using this interrupt-names property to do so.
|
||||
- interrupts
|
||||
Array of interrupt specifiers.
|
||||
Must contain one entry per entry in the interrupt-names property,
|
||||
in a matching order.
|
||||
- #mbox-cells : Should be 2.
|
||||
|
||||
The mbox specifier of the "mboxes" property in the client node should contain
|
||||
two cells. The first cell determines the HSP type and the second cell is used
|
||||
to identify the mailbox that the client is going to use.
|
||||
|
||||
For doorbells, the second cell specifies the index of the doorbell to use.
|
||||
|
||||
For shared mailboxes, the second cell is composed of two fields:
|
||||
- bits 31..24:
|
||||
A bit mask of flags that further specify how the shared mailbox will be
|
||||
used. Valid flags are:
|
||||
- bit 31:
|
||||
Defines the direction of the mailbox. If set, the mailbox will be used
|
||||
as a producer (i.e. used to send data). If cleared, the mailbox is the
|
||||
consumer of data sent by a producer.
|
||||
|
||||
- bits 23.. 0:
|
||||
The index of the shared mailbox to use. The number of available mailboxes
|
||||
may vary by instance of the HSP block and SoC generation.
|
||||
|
||||
The following file contains definitions that can be used to construct mailbox
|
||||
specifiers:
|
||||
|
||||
<dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
Example:
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x0 0x03c00000 0x0 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
client {
|
||||
...
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>;
|
||||
};
|
||||
@ -0,0 +1,114 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Hardware Synchronization Primitives (HSP)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The HSP modules are used for the processors to share resources and
|
||||
communicate together. It provides a set of hardware synchronization
|
||||
primitives for interprocessor communication. So the interprocessor
|
||||
communication (IPC) protocols can use hardware synchronization
|
||||
primitives, when operating between two processors not in an SMP
|
||||
relationship.
|
||||
|
||||
The features that HSP supported are shared mailboxes, shared
|
||||
semaphores, arbitrated semaphores and doorbells.
|
||||
|
||||
The mbox specifier of the "mboxes" property in the client node should
|
||||
contain two cells. The first cell determines the HSP type and the
|
||||
second cell is used to identify the mailbox that the client is going
|
||||
to use.
|
||||
|
||||
For doorbells, the second cell specifies the index of the doorbell to
|
||||
use.
|
||||
|
||||
For shared mailboxes, the second cell is composed of two fields:
|
||||
- bits 31..24:
|
||||
A bit mask of flags that further specify how the shared mailbox
|
||||
will be used. Valid flags are:
|
||||
- bit 31:
|
||||
Defines the direction of the mailbox. If set, the mailbox
|
||||
will be used as a producer (i.e. used to send data). If
|
||||
cleared, the mailbox is the consumer of data sent by a
|
||||
producer.
|
||||
|
||||
- bits 23..0:
|
||||
The index of the shared mailbox to use. The number of available
|
||||
mailboxes may vary by instance of the HSP block and SoC
|
||||
generation.
|
||||
|
||||
The following file contains definitions that can be used to
|
||||
construct mailbox specifiers:
|
||||
|
||||
<dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^hsp@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra186-hsp
|
||||
- const: nvidia,tegra194-hsp
|
||||
- items:
|
||||
- const: nvidia,tegra234-hsp
|
||||
- const: nvidia,tegra194-hsp
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
interrupt-names:
|
||||
oneOf:
|
||||
# shared interrupts are optional
|
||||
- items:
|
||||
- const: doorbell
|
||||
|
||||
- items:
|
||||
- const: doorbell
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
|
||||
- items:
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
- pattern: "^shared[0-7]$"
|
||||
|
||||
"#mbox-cells":
|
||||
const: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x03c00000 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
client {
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
|
||||
};
|
||||
@ -1,64 +0,0 @@
|
||||
NVIDIA Tegra Video Decoder Engine
|
||||
|
||||
Required properties:
|
||||
- compatible : Must contain one of the following values:
|
||||
- "nvidia,tegra20-vde"
|
||||
- "nvidia,tegra30-vde"
|
||||
- "nvidia,tegra114-vde"
|
||||
- "nvidia,tegra124-vde"
|
||||
- "nvidia,tegra132-vde"
|
||||
- reg : Must contain an entry for each entry in reg-names.
|
||||
- reg-names : Must include the following entries:
|
||||
- sxe
|
||||
- bsev
|
||||
- mbe
|
||||
- ppe
|
||||
- mce
|
||||
- tfe
|
||||
- ppb
|
||||
- vdma
|
||||
- frameid
|
||||
- iram : Must contain phandle to the mmio-sram device node that represents
|
||||
IRAM region used by VDE.
|
||||
- interrupts : Must contain an entry for each entry in interrupt-names.
|
||||
- interrupt-names : Must include the following entries:
|
||||
- sync-token
|
||||
- bsev
|
||||
- sxe
|
||||
- clocks : Must include the following entries:
|
||||
- vde
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
- reset-names : Should include the following entries:
|
||||
- vde
|
||||
|
||||
Optional properties:
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
- reset-names : Must include the following entries:
|
||||
- mc
|
||||
- iommus: Must contain phandle to the IOMMU device node.
|
||||
|
||||
Example:
|
||||
|
||||
video-codec@6001a000 {
|
||||
compatible = "nvidia,tegra20-vde";
|
||||
reg = <0x6001a000 0x1000 /* Syntax Engine */
|
||||
0x6001b000 0x1000 /* Video Bitstream Engine */
|
||||
0x6001c000 0x100 /* Macroblock Engine */
|
||||
0x6001c200 0x100 /* Post-processing Engine */
|
||||
0x6001c400 0x100 /* Motion Compensation Engine */
|
||||
0x6001c600 0x100 /* Transform Engine */
|
||||
0x6001c800 0x100 /* Pixel prediction block */
|
||||
0x6001ca00 0x100 /* Video DMA */
|
||||
0x6001d800 0x300 /* Video frame controls */>;
|
||||
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
|
||||
"tfe", "ppb", "vdma", "frameid";
|
||||
iram = <&vde_pool>; /* IRAM region */
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
|
||||
interrupt-names = "sync-token", "bsev", "sxe";
|
||||
clocks = <&tegra_car TEGRA20_CLK_VDE>;
|
||||
reset-names = "vde", "mc";
|
||||
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
|
||||
iommus = <&mc TEGRA_SWGROUP_VDE>;
|
||||
};
|
||||
119
Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml
Normal file
119
Documentation/devicetree/bindings/media/nvidia,tegra-vde.yaml
Normal file
@ -0,0 +1,119 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Video Decoder Engine
|
||||
|
||||
maintainers:
|
||||
- Dmitry Osipenko <digetx@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra132-vde
|
||||
- nvidia,tegra124-vde
|
||||
- nvidia,tegra114-vde
|
||||
- items:
|
||||
- const: nvidia,tegra30-vde
|
||||
- const: nvidia,tegra20-vde
|
||||
- items:
|
||||
- const: nvidia,tegra20-vde
|
||||
|
||||
reg:
|
||||
maxItems: 9
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: sxe
|
||||
- const: bsev
|
||||
- const: mbe
|
||||
- const: ppe
|
||||
- const: mce
|
||||
- const: tfe
|
||||
- const: ppb
|
||||
- const: vdma
|
||||
- const: frameid
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: vde
|
||||
- const: mc
|
||||
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: sync-token
|
||||
- const: bsev
|
||||
- const: sxe
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
iram:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle of the SRAM MMIO node.
|
||||
|
||||
operating-points-v2:
|
||||
description:
|
||||
Should contain freqs and voltages and opp-supported-hw property,
|
||||
which is a bitfield indicating SoC speedo or process ID mask.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to the SoC core power domain.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
video-codec@6001a000 {
|
||||
compatible = "nvidia,tegra20-vde";
|
||||
reg = <0x6001a000 0x1000>, /* Syntax Engine */
|
||||
<0x6001b000 0x1000>, /* Video Bitstream Engine */
|
||||
<0x6001c000 0x100>, /* Macroblock Engine */
|
||||
<0x6001c200 0x100>, /* Post-processing Engine */
|
||||
<0x6001c400 0x100>, /* Motion Compensation Engine */
|
||||
<0x6001c600 0x100>, /* Transform Engine */
|
||||
<0x6001c800 0x100>, /* Pixel prediction block */
|
||||
<0x6001ca00 0x100>, /* Video DMA */
|
||||
<0x6001d800 0x300>; /* Video frame controls */
|
||||
reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
|
||||
"tfe", "ppb", "vdma", "frameid";
|
||||
iram = <&iram>; /* IRAM MMIO region */
|
||||
interrupts = <0 9 4>, /* Sync token */
|
||||
<0 10 4>, /* BSE-V */
|
||||
<0 12 4>; /* SXE */
|
||||
interrupt-names = "sync-token", "bsev", "sxe";
|
||||
clocks = <&clk 61>;
|
||||
reset-names = "vde", "mc";
|
||||
resets = <&rst 61>, <&mem 13>;
|
||||
iommus = <&mem 15>;
|
||||
operating-points-v2 = <&dvfs_opp_table>;
|
||||
power-domains = <&domain>;
|
||||
};
|
||||
@ -31,12 +31,15 @@ properties:
|
||||
- enum:
|
||||
- nvidia,tegra186-mc
|
||||
- nvidia,tegra194-mc
|
||||
- nvidia,tegra234-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: MC general interrupt
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
@ -48,6 +51,9 @@ properties:
|
||||
|
||||
dma-ranges: true
|
||||
|
||||
"#interconnect-cells":
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
"^external-memory-controller@[0-9a-f]+$":
|
||||
description:
|
||||
@ -63,12 +69,15 @@ patternProperties:
|
||||
- enum:
|
||||
- nvidia,tegra186-emc
|
||||
- nvidia,tegra194-emc
|
||||
- nvidia,tegra234-emc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: EMC general interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
@ -78,11 +87,83 @@ patternProperties:
|
||||
items:
|
||||
- const: emc
|
||||
|
||||
"#interconnect-cells":
|
||||
const: 0
|
||||
|
||||
nvidia,bpmp:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle of the node representing the BPMP
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra234-emc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#interconnect-cells"
|
||||
- nvidia,bpmp
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra234-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -90,8 +171,6 @@ required:
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
@ -124,12 +203,9 @@ examples:
|
||||
clocks = <&bpmp TEGRA186_CLK_EMC>;
|
||||
clock-names = "emc";
|
||||
|
||||
#interconnect-cells = <0>;
|
||||
|
||||
nvidia,bpmp = <&bpmp>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bpmp: bpmp {
|
||||
compatible = "nvidia,tegra186-bpmp";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
@ -24,17 +24,23 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-rpc-if # RZ/G2M
|
||||
- renesas,r8a774b1-rpc-if # RZ/G2N
|
||||
- renesas,r8a774c0-rpc-if # RZ/G2E
|
||||
- renesas,r8a774e1-rpc-if # RZ/G2H
|
||||
- renesas,r8a77970-rpc-if # R-Car V3M
|
||||
- renesas,r8a77980-rpc-if # R-Car V3H
|
||||
- renesas,r8a77995-rpc-if # R-Car D3
|
||||
- renesas,r8a779a0-rpc-if # R-Car V3U
|
||||
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2 device
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-rpc-if # RZ/G2M
|
||||
- renesas,r8a774b1-rpc-if # RZ/G2N
|
||||
- renesas,r8a774c0-rpc-if # RZ/G2E
|
||||
- renesas,r8a774e1-rpc-if # RZ/G2H
|
||||
- renesas,r8a77970-rpc-if # R-Car V3M
|
||||
- renesas,r8a77980-rpc-if # R-Car V3H
|
||||
- renesas,r8a77995-rpc-if # R-Car D3
|
||||
- renesas,r8a779a0-rpc-if # R-Car V3U
|
||||
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 or RZ/G2{E,H,M,N} device
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
|
||||
- const: renesas,rzg2l-rpc-if # RZ/G2L family
|
||||
|
||||
reg:
|
||||
items:
|
||||
@ -48,7 +54,9 @@ properties:
|
||||
- const: dirmap
|
||||
- const: wbuf
|
||||
|
||||
clocks:
|
||||
clocks: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
@ -67,8 +75,6 @@ patternProperties:
|
||||
- cfi-flash
|
||||
- jedec,spi-nor
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@ -79,6 +85,26 @@ required:
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,rzg2l-rpc-if
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: SPI Multi IO Register access clock (SPI_CLK2)
|
||||
- description: SPI Multi IO Main clock (SPI_CLK).
|
||||
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
NVIDIA Tegra186 (and later) MISC register block
|
||||
|
||||
The MISC register block found on Tegra186 and later SoCs contains registers
|
||||
that can be used to identify a given chip and various strapping options.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- Tegra186: "nvidia,tegra186-misc"
|
||||
- Tegra194: "nvidia,tegra194-misc"
|
||||
- Tegra234: "nvidia,tegra234-misc"
|
||||
- reg: Should contain 2 entries: The first entry gives the physical address
|
||||
and length of the register region which contains revision and debug
|
||||
features. The second entry specifies the physical address and length
|
||||
of the register region indicating the strapping options.
|
||||
@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/nvidia,tegra186-misc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 (and later) MISC register block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The MISC register block found on Tegra186 and later SoCs contains
|
||||
registers that can be used to identify a given chip and various strapping
|
||||
options.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-misc
|
||||
- nvidia,tegra194-misc
|
||||
- nvidia,tegra234-misc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: physical address and length of the registers which
|
||||
contain revision and debug features
|
||||
- description: physical address and length of the registers which
|
||||
indicate strapping options
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
misc@100000 {
|
||||
compatible = "nvidia,tegra186-misc";
|
||||
reg = <0x00100000 0xf000>,
|
||||
<0x0010f000 0x1000>;
|
||||
};
|
||||
@ -1,17 +0,0 @@
|
||||
NVIDIA Tegra APBMISC block
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- Tegra20: "nvidia,tegra20-apbmisc"
|
||||
- Tegra30: "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra114: "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra124: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra132: "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- Tegra210: "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"
|
||||
- reg: Should contain 2 entries: the first entry gives the physical address
|
||||
and length of the registers which contain revision and debug features.
|
||||
The second entry gives the physical address and length of the
|
||||
registers indicating the strapping options.
|
||||
|
||||
Optional properties:
|
||||
- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).
|
||||
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/misc/nvidia,tegra20-apbmisc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra APBMISC block
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra210-apbmisc
|
||||
- nvidia,tegra124-apbmisc
|
||||
- nvidia,tegra114-apbmisc
|
||||
- nvidia,tegra30-apbmisc
|
||||
- const: nvidia,tegra20-apbmisc
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra20-apbmisc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: physical address and length of the registers which
|
||||
contain revision and debug features
|
||||
- description: physical address and length of the registers which
|
||||
indicate strapping options
|
||||
|
||||
nvidia,long-ram-code:
|
||||
description: If present, the RAM code is long (4 bit). If not, short
|
||||
(2 bit).
|
||||
type: boolean
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
apbmisc@70000800 {
|
||||
compatible = "nvidia,tegra20-apbmisc";
|
||||
reg = <0x70000800 0x64>, /* Chip revision */
|
||||
<0x70000008 0x04>; /* Strapping options */
|
||||
};
|
||||
@ -1,143 +0,0 @@
|
||||
* NVIDIA Tegra Secure Digital Host Controller
|
||||
|
||||
This controller on Tegra family SoCs provides an interface for MMC, SD,
|
||||
and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the sdhci-tegra driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of:
|
||||
- "nvidia,tegra20-sdhci": for Tegra20
|
||||
- "nvidia,tegra30-sdhci": for Tegra30
|
||||
- "nvidia,tegra114-sdhci": for Tegra114
|
||||
- "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
|
||||
- "nvidia,tegra210-sdhci": for Tegra210
|
||||
- "nvidia,tegra186-sdhci": for Tegra186
|
||||
- "nvidia,tegra194-sdhci": for Tegra194
|
||||
- clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
|
||||
One for the module clock and one for the timeout clock.
|
||||
For all other Tegra devices, must contain a single entry for
|
||||
the module clock. See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
|
||||
strings 'sdhci' and 'tmclk' to represent the module and
|
||||
the timeout clocks, respectively.
|
||||
For all other Tegra devices must contain the string 'sdhci'
|
||||
to represent the module clock.
|
||||
- resets : Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names : Must include the following entries:
|
||||
- sdhci
|
||||
|
||||
Optional properties:
|
||||
- power-gpios : Specify GPIOs for power control
|
||||
|
||||
Example:
|
||||
|
||||
sdhci@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
Optional properties for Tegra210, Tegra186 and Tegra194:
|
||||
- pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
|
||||
configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
|
||||
for controllers supporting multiple voltage levels. The order of names
|
||||
should correspond to the pin configuration states in pinctrl-0 and
|
||||
pinctrl-1.
|
||||
- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
|
||||
Tegra210 where pad config registers are in the pinmux register domain
|
||||
for pull-up-strength and pull-down-strength values configuration when
|
||||
using pads at 3V3 and 1V8 levels.
|
||||
- nvidia,only-1-8-v : The presence of this property indicates that the
|
||||
controller operates at a 1.8 V fixed I/O voltage.
|
||||
- nvidia,pad-autocal-pull-up-offset-3v3,
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
|
||||
calibration offsets for 3.3 V signaling modes.
|
||||
- nvidia,pad-autocal-pull-up-offset-1v8,
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
|
||||
calibration offsets for 1.8 V signaling modes.
|
||||
- nvidia,pad-autocal-pull-up-offset-3v3-timeout,
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
|
||||
strength used as a fallback in case the automatic calibration times
|
||||
out on a 3.3 V signaling mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-1v8-timeout,
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
|
||||
strength used as a fallback in case the automatic calibration times
|
||||
out on a 1.8 V signaling mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-sdr104,
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
|
||||
calibration offsets for SDR104 mode.
|
||||
- nvidia,pad-autocal-pull-up-offset-hs400,
|
||||
nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
|
||||
calibration offsets for HS400 mode.
|
||||
- nvidia,default-tap : Specify the default inbound sampling clock
|
||||
trimmer value for non-tunable modes.
|
||||
- nvidia,default-trim : Specify the default outbound clock trimmer
|
||||
value.
|
||||
- nvidia,dqs-trim : Specify DQS trim value for HS400 timing
|
||||
|
||||
Notes on the pad calibration pull up and pulldown offset values:
|
||||
- The property values are drive codes which are programmed into the
|
||||
PD_OFFSET and PU_OFFSET sections of the
|
||||
SDHCI_TEGRA_AUTO_CAL_CONFIG register.
|
||||
- A higher value corresponds to higher drive strength. Please refer
|
||||
to the reference manual of the SoC for correct values.
|
||||
- The SDR104 and HS400 timing specific values are used in
|
||||
corresponding modes if specified.
|
||||
|
||||
Notes on tap and trim values:
|
||||
- The values are used for compensating trace length differences
|
||||
by adjusting the sampling point.
|
||||
- The values are programmed to the Vendor Clock Control Register.
|
||||
Please refer to the reference manual of the SoC for correct
|
||||
values.
|
||||
- The DQS trim values are only used on controllers which support
|
||||
HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
|
||||
HS400.
|
||||
|
||||
Example:
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
|
||||
clock-names = "sdhci";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x0 0x700b0000 0x0 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
status = "disabled";
|
||||
};
|
||||
317
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
Normal file
317
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
Normal file
@ -0,0 +1,317 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Secure Digital Host Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
This controller on Tegra family SoCs provides an interface for MMC, SD, and
|
||||
SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described by
|
||||
mmc-controller.yaml and the properties for the Tegra SDHCI controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
- nvidia,tegra210-sdhci
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra132-sdhci
|
||||
- const: nvidia,tegra124-sdhci
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra194-sdhci
|
||||
- nvidia,tegra234-sdhci
|
||||
- const: nvidia,tegra186-sdhci
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
assigned-clocks: true
|
||||
assigned-clock-parents: true
|
||||
assigned-clock-rates: true
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
|
||||
power-gpios:
|
||||
description: specify GPIOs for power control
|
||||
maxItems: 1
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
operating-points-v2:
|
||||
$ref: "/schemas/types.yaml#/definitions/phandle"
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
nvidia,default-tap:
|
||||
description: Specify the default inbound sampling clock trimmer value for
|
||||
non-tunable modes.
|
||||
|
||||
The values are used for compensating trace length differences by
|
||||
adjusting the sampling point. The values are programmed to the Vendor
|
||||
Clock Control Register. Please refer to the reference manual of the SoC
|
||||
for correct values.
|
||||
|
||||
The DQS trim values are only used on controllers which support HS400
|
||||
timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,default-trim:
|
||||
description: Specify the default outbound clock trimmer value.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,dqs-trim:
|
||||
description: Specify DQS trim value for HS400 timing.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-down-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8:
|
||||
description: Specify drive strength calibration offsets for 1.8 V
|
||||
signaling modes.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-1v8-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 1.8 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3:
|
||||
description: Specify drive strength calibration offsets for 3.3 V
|
||||
signaling modes.
|
||||
|
||||
The property values are drive codes which are programmed into the
|
||||
PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
|
||||
register. A higher value corresponds to higher drive strength. Please
|
||||
refer to the reference manual of the SoC for correct values. The SDR104
|
||||
and HS400 timing specific values are used in corresponding modes if
|
||||
specified.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-3v3-timeout:
|
||||
description: Specify drive strength used as a fallback in case the
|
||||
automatic calibration times out on a 3.3 V signaling mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-sdr104:
|
||||
description: Specify drive strength calibration offsets for SDR104 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,pad-autocal-pull-up-offset-hs400:
|
||||
description: Specify drive strength calibration offsets for HS400 mode.
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
|
||||
nvidia,only-1-8v:
|
||||
description: The presence of this property indicates that the controller
|
||||
operates at a 1.8 V fixed I/O voltage.
|
||||
$ref: "/schemas/types.yaml#/definitions/flag"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: "mmc-controller.yaml"
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra20-sdhci
|
||||
- nvidia,tegra30-sdhci
|
||||
- nvidia,tegra114-sdhci
|
||||
- nvidia,tegra124-sdhci
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
minItems: 1
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: module clock
|
||||
- description: timeout clock
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
items:
|
||||
- const: sdhci
|
||||
- const: tmclk
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: nvidia,tegra210-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-3v3-drv
|
||||
description: pull-up/down configuration for 3.3 V
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
- items:
|
||||
- const: sdmmc-1v8-drv
|
||||
description: pull-up/down configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra186-sdhci
|
||||
- nvidia,tegra194-sdhci
|
||||
then:
|
||||
properties:
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: sdmmc-3v3
|
||||
description: pad configuration for 3.3 V
|
||||
- const: sdmmc-1v8
|
||||
description: pad configuration for 1.8 V
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@c8000200 {
|
||||
compatible = "nvidia,tegra20-sdhci";
|
||||
reg = <0xc8000200 0x200>;
|
||||
interrupts = <47>;
|
||||
clocks = <&tegra_car 14>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
|
||||
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
|
||||
power-gpios = <&gpio 155 0>; /* gpio PT3 */
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mmc@700b0000 {
|
||||
compatible = "nvidia,tegra210-sdhci";
|
||||
reg = <0x700b0000 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
|
||||
<&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
|
||||
clock-names = "sdhci", "tmclk";
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
|
||||
"sdmmc-3v3-drv", "sdmmc-1v8-drv";
|
||||
pinctrl-0 = <&sdmmc1_3v3>;
|
||||
pinctrl-1 = <&sdmmc1_1v8>;
|
||||
pinctrl-2 = <&sdmmc1_3v3_drv>;
|
||||
pinctrl-3 = <&sdmmc1_1v8_drv>;
|
||||
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
|
||||
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
|
||||
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
|
||||
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
|
||||
nvidia,default-tap = <0x2>;
|
||||
nvidia,default-trim = <0x4>;
|
||||
assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_C4>;
|
||||
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
|
||||
assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
|
||||
};
|
||||
@ -113,31 +113,51 @@ allOf:
|
||||
clocks:
|
||||
items:
|
||||
- description: IMCLK, SDHI channel main clock1.
|
||||
- description: CLK_HS, SDHI channel High speed clock which operates
|
||||
4 times that of SDHI channel main clock1.
|
||||
- description: IMCLK2, SDHI channel main clock2. When this clock is
|
||||
turned off, external SD card detection cannot be
|
||||
detected.
|
||||
- description: CLK_HS, SDHI channel High speed clock which operates
|
||||
4 times that of SDHI channel main clock1.
|
||||
- description: ACLK, SDHI channel bus clock.
|
||||
clock-names:
|
||||
items:
|
||||
- const: imclk
|
||||
- const: imclk2
|
||||
- const: clk_hs
|
||||
- const: core
|
||||
- const: clkh
|
||||
- const: cd
|
||||
- const: aclk
|
||||
required:
|
||||
- clock-names
|
||||
- resets
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: cd
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,rcar-gen2-sdhi
|
||||
- renesas,rcar-gen3-sdhi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 1
|
||||
uniqueItems: true
|
||||
items:
|
||||
- const: core
|
||||
- enum: [ clkh, cd ]
|
||||
- const: cd
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: cd
|
||||
|
||||
- if:
|
||||
properties:
|
||||
|
||||
@ -28,19 +28,17 @@ description: |
|
||||
distributed over the root ports as the OS sees fit by programming
|
||||
the PCIe controller's port registers.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: apple,t8103-pcie
|
||||
- enum:
|
||||
- apple,t8103-pcie
|
||||
- apple,t6000-pcie
|
||||
- const: apple,pcie
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 5
|
||||
maxItems: 6
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
@ -50,6 +48,7 @@ properties:
|
||||
- const: port0
|
||||
- const: port1
|
||||
- const: port2
|
||||
- const: port3
|
||||
|
||||
ranges:
|
||||
minItems: 2
|
||||
@ -59,7 +58,7 @@ properties:
|
||||
description:
|
||||
Interrupt specifiers, one for each root port.
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
maxItems: 4
|
||||
|
||||
msi-parent: true
|
||||
|
||||
@ -81,6 +80,21 @@ required:
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: apple,t8103-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 5
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/apple-aic.h>
|
||||
|
||||
@ -12,12 +12,14 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: arm,cmn-600
|
||||
enum:
|
||||
- arm,cmn-600
|
||||
- arm,ci-700
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Physical address of the base (PERIPHBASE) and
|
||||
size (up to 64MB) of the configuration address space.
|
||||
size of the configuration address space.
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
@ -31,14 +33,23 @@ properties:
|
||||
|
||||
arm,root-node:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Offset from PERIPHBASE of the configuration
|
||||
discovery node (see TRM definition of ROOTNODEBASE).
|
||||
description: Offset from PERIPHBASE of CMN-600's configuration
|
||||
discovery node (see TRM definition of ROOTNODEBASE). Not
|
||||
relevant for newer CMN/CI products.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- arm,root-node
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: arm,cmn-600
|
||||
then:
|
||||
required:
|
||||
- arm,root-node
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
70
Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml
Normal file
70
Documentation/devicetree/bindings/perf/arm,smmu-v3-pmcg.yaml
Normal file
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Arm SMMUv3 Performance Monitor Counter Group
|
||||
|
||||
maintainers:
|
||||
- Will Deacon <will@kernel.org>
|
||||
- Robin Murphy <robin.murphy@arm.com>
|
||||
|
||||
description: |
|
||||
An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
|
||||
They are standalone performance monitoring units that support both
|
||||
architected and IMPLEMENTATION DEFINED event counters.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^pmu@[0-9a-f]*"
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: arm,mmu-600-pmcg
|
||||
- const: arm,smmu-v3-pmcg
|
||||
- const: arm,smmu-v3-pmcg
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Register page 0
|
||||
- description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
msi-parent: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
anyOf:
|
||||
- required:
|
||||
- interrupts
|
||||
- required:
|
||||
- msi-parent
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
pmu@2b420000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x2b420000 0x1000>,
|
||||
<0x2b430000 0x1000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-parent = <&its 0xff0000>;
|
||||
};
|
||||
|
||||
pmu@2b440000 {
|
||||
compatible = "arm,smmu-v3-pmcg";
|
||||
reg = <0x2b440000 0x1000>,
|
||||
<0x2b450000 0x1000>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
|
||||
msi-parent = <&its 0xff0000>;
|
||||
};
|
||||
@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell CN10K LLC-TAD performance monitor
|
||||
|
||||
maintainers:
|
||||
- Bhaskara Budiredla <bbudiredla@marvell.com>
|
||||
|
||||
description: |
|
||||
The Tag-and-Data units (TADs) maintain coherence and contain CN10K
|
||||
shared on-chip last level cache (LLC). The tad pmu measures the
|
||||
performance of last-level cache. Each tad pmu supports up to eight
|
||||
counters.
|
||||
|
||||
The DT setup comprises of number of tad blocks, the sizes of pmu
|
||||
regions, tad blocks and overall base address of the HW.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,cn10k-tad-pmu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
marvell,tad-cnt:
|
||||
description: specifies the number of tads on the soc
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
marvell,tad-page-size:
|
||||
description: specifies the size of each tad page
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
marvell,tad-pmu-page-size:
|
||||
description: specifies the size of page that the pmu uses
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- marvell,tad-cnt
|
||||
- marvell,tad-page-size
|
||||
- marvell,tad-pmu-page-size
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
||||
tad {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
tad_pmu@80000000 {
|
||||
compatible = "marvell,cn10k-tad-pmu";
|
||||
reg = <0x87e2 0x80000000 0x0 0x1000>;
|
||||
marvell,tad-cnt = <1>;
|
||||
marvell,tad-page-size = <0x1000>;
|
||||
marvell,tad-pmu-page-size = <0x1000>;
|
||||
};
|
||||
};
|
||||
@ -17,7 +17,9 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: apple,t8103-pinctrl
|
||||
- enum:
|
||||
- apple,t8103-pinctrl
|
||||
- apple,t6000-pinctrl
|
||||
- const: apple,pinctrl
|
||||
|
||||
reg:
|
||||
@ -50,6 +52,9 @@ properties:
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
|
||||
@ -0,0 +1,307 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7100 Pin Controller Device Tree Bindings
|
||||
|
||||
description: |
|
||||
Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
|
||||
|
||||
Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
|
||||
and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
|
||||
configurable bias, drive strength, schmitt trigger etc. The SoC has an
|
||||
interesting 2-layered approach to pin muxing best illustrated by the diagram
|
||||
below.
|
||||
|
||||
Signal group 0, 1, ... or 6
|
||||
___|___
|
||||
| |
|
||||
LCD output -----------------| |
|
||||
CMOS Camera interface ------| |--- PAD_GPIO[0]
|
||||
Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
|
||||
... | | ...
|
||||
| |--- PAD_GPIO[63]
|
||||
-------- GPIO0 ------------| |
|
||||
| -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0]
|
||||
| | | | | |--- PAD_FUNC_SHARE[1]
|
||||
| | | | ... | | ...
|
||||
| | | | | |--- PAD_FUNC_SHARE[141]
|
||||
| | -----|---|-- GPIO63 ---| |
|
||||
| | | | | | -------
|
||||
UART0 UART1 --
|
||||
|
||||
|
||||
The big MUX in the diagram only has 7 different ways of mapping peripherals
|
||||
on the left to pins on the right. StarFive calls the 7 configurations "signal
|
||||
groups".
|
||||
However some peripherals have their I/O go through the 64 "GPIOs". The
|
||||
diagram only shows UART0 and UART1, but this also includes a number of other
|
||||
UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
|
||||
GPIOs such that any GPIO can be set up to be controlled by any of the
|
||||
peripherals.
|
||||
Note that signal group 0 doesn't map any of the GPIOs to pins, and only
|
||||
signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
|
||||
|
||||
maintainers:
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
- Drew Fustini <drew@beagleboard.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7100-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: gpio
|
||||
- const: padctl
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: The GPIO parent interrupt.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
starfive,signal-group:
|
||||
description: |
|
||||
Select one of the 7 signal groups. If this property is not set it
|
||||
defaults to the configuration already chosen by the earlier boot stages.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- "#interrupt-cells"
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
type: object
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnode representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to
|
||||
muxer configuration, bias, input enable/disable, input schmitt
|
||||
trigger enable/disable, slew-rate and drive strength.
|
||||
$ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description: |
|
||||
The list of pin identifiers that properties in the node apply to.
|
||||
This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
|
||||
macros.
|
||||
Either this or "pinmux" has to be specified, but not both.
|
||||
$ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pins"
|
||||
|
||||
pinmux:
|
||||
description: |
|
||||
The list of GPIOs and their mux settings that properties in the
|
||||
node apply to. This should be set using the GPIOMUX macro.
|
||||
Either this or "pins" has to be specified, but not both.
|
||||
$ref: "/schemas/pinctrl/pinmux-node.yaml#/properties/pinmux"
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up:
|
||||
type: boolean
|
||||
|
||||
bias-pull-down:
|
||||
type: boolean
|
||||
|
||||
drive-strength:
|
||||
enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
slew-rate:
|
||||
maximum: 7
|
||||
|
||||
starfive,strong-pull-up:
|
||||
description: enable strong pull-up.
|
||||
type: boolean
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/starfive-jh7100.h>
|
||||
#include <dt-bindings/reset/starfive-jh7100.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-starfive.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pinctrl@11910000 {
|
||||
compatible = "starfive,jh7100-pinctrl";
|
||||
reg = <0x0 0x11910000 0x0 0x10000>,
|
||||
<0x0 0x11858000 0x0 0x1000>;
|
||||
reg-names = "gpio", "padctl";
|
||||
clocks = <&clkgen JH7100_CLK_GPIO_APB>;
|
||||
resets = <&clkgen JH7100_RSTN_GPIO_APB>;
|
||||
interrupts = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
starfive,signal-group = <6>;
|
||||
|
||||
gmac_pins_default: gmac-0 {
|
||||
gtxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(115)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <35>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
miitxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(116)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
tx-pins {
|
||||
pins = <PAD_FUNC_SHARE(117)>,
|
||||
<PAD_FUNC_SHARE(119)>,
|
||||
<PAD_FUNC_SHARE(120)>,
|
||||
<PAD_FUNC_SHARE(121)>,
|
||||
<PAD_FUNC_SHARE(122)>,
|
||||
<PAD_FUNC_SHARE(123)>,
|
||||
<PAD_FUNC_SHARE(124)>,
|
||||
<PAD_FUNC_SHARE(125)>,
|
||||
<PAD_FUNC_SHARE(126)>;
|
||||
bias-disable;
|
||||
drive-strength = <35>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
rxclk-pins {
|
||||
pins = <PAD_FUNC_SHARE(127)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <6>;
|
||||
};
|
||||
rxer-pins {
|
||||
pins = <PAD_FUNC_SHARE(129)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
rx-pins {
|
||||
pins = <PAD_FUNC_SHARE(128)>,
|
||||
<PAD_FUNC_SHARE(130)>,
|
||||
<PAD_FUNC_SHARE(131)>,
|
||||
<PAD_FUNC_SHARE(132)>,
|
||||
<PAD_FUNC_SHARE(133)>,
|
||||
<PAD_FUNC_SHARE(134)>,
|
||||
<PAD_FUNC_SHARE(135)>,
|
||||
<PAD_FUNC_SHARE(136)>,
|
||||
<PAD_FUNC_SHARE(137)>,
|
||||
<PAD_FUNC_SHARE(138)>,
|
||||
<PAD_FUNC_SHARE(139)>,
|
||||
<PAD_FUNC_SHARE(140)>,
|
||||
<PAD_FUNC_SHARE(141)>;
|
||||
bias-pull-up;
|
||||
drive-strength = <14>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0_pins_default: i2c0-0 {
|
||||
i2c-pins {
|
||||
pinmux = <GPIOMUX(62, GPO_LOW,
|
||||
GPO_I2C0_PAD_SCK_OEN,
|
||||
GPI_I2C0_PAD_SCK_IN)>,
|
||||
<GPIOMUX(61, GPO_LOW,
|
||||
GPO_I2C0_PAD_SDA_OEN,
|
||||
GPI_I2C0_PAD_SDA_IN)>;
|
||||
bias-disable; /* external pull-up */
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
};
|
||||
|
||||
uart3_pins_default: uart3-0 {
|
||||
rx-pins {
|
||||
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
|
||||
GPI_UART3_PAD_SIN)>;
|
||||
bias-pull-up;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
};
|
||||
tx-pins {
|
||||
pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
|
||||
GPO_ENABLE, GPI_NONE)>;
|
||||
bias-disable;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
pinctrl-0 = <&gmac_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl-0 = <&uart3_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,79 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/power/apple,pmgr-pwrstate.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoC PMGR Power States
|
||||
|
||||
maintainers:
|
||||
- Hector Martin <marcan@marcan.st>
|
||||
|
||||
allOf:
|
||||
- $ref: "power-domain.yaml#"
|
||||
|
||||
description: |
|
||||
Apple SoCs include PMGR blocks responsible for power management,
|
||||
which can control various clocks, resets, power states, and
|
||||
performance features. This binding describes the device power
|
||||
state registers, which control power states and resets.
|
||||
|
||||
Each instance of a power controller within the PMGR syscon node
|
||||
represents a generic power domain provider, as documented in
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
The provider controls a single SoC block. The power hierarchy is
|
||||
represented via power-domains relationships between these nodes.
|
||||
|
||||
See Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml
|
||||
for the top-level PMGR node documentation.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,t8103-pmgr-pwrstate
|
||||
- apple,t6000-pmgr-pwrstate
|
||||
- const: apple,pmgr-pwrstate
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#power-domain-cells":
|
||||
const: 0
|
||||
|
||||
"#reset-cells":
|
||||
const: 0
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
Reference to parent power domains. A domain may have multiple parents,
|
||||
and all will be powered up when it is powered.
|
||||
minItems: 1
|
||||
maxItems: 8 # Arbitrary, should be enough
|
||||
|
||||
label:
|
||||
description:
|
||||
Specifies the name of the SoC domain being controlled. This is used to
|
||||
name the power/reset domains.
|
||||
|
||||
apple,always-on:
|
||||
description:
|
||||
Forces this power domain to always be powered up.
|
||||
type: boolean
|
||||
|
||||
apple,min-state:
|
||||
description:
|
||||
Specifies the minimum power state for auto-PM.
|
||||
0 = power gated, 4 = clock gated, 15 = on.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
minimum: 0
|
||||
maximum: 15
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#power-domain-cells"
|
||||
- "#reset-cells"
|
||||
- label
|
||||
|
||||
additionalProperties: false
|
||||
@ -24,6 +24,7 @@ properties:
|
||||
- qcom,msm8994-rpmpd
|
||||
- qcom,msm8996-rpmpd
|
||||
- qcom,msm8998-rpmpd
|
||||
- qcom,qcm2290-rpmpd
|
||||
- qcom,qcs404-rpmpd
|
||||
- qcom,sdm660-rpmpd
|
||||
- qcom,sc7180-rpmhpd
|
||||
@ -32,10 +33,12 @@ properties:
|
||||
- qcom,sdm845-rpmhpd
|
||||
- qcom,sdx55-rpmhpd
|
||||
- qcom,sm6115-rpmpd
|
||||
- qcom,sm6125-rpmpd
|
||||
- qcom,sm6350-rpmhpd
|
||||
- qcom,sm8150-rpmhpd
|
||||
- qcom,sm8250-rpmhpd
|
||||
- qcom,sm8350-rpmhpd
|
||||
- qcom,sm8450-rpmhpd
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
@ -41,6 +41,7 @@ properties:
|
||||
- renesas,r8a77990-sysc # R-Car E3
|
||||
- renesas,r8a77995-sysc # R-Car D3
|
||||
- renesas,r8a779a0-sysc # R-Car V3U
|
||||
- renesas,r8a779f0-sysc # R-Car S4-8
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -48,6 +48,7 @@ properties:
|
||||
- renesas,r8a77990-rst # R-Car E3
|
||||
- renesas,r8a77995-rst # R-Car D3
|
||||
- renesas,r8a779a0-rst # R-Car V3U
|
||||
- renesas,r8a779f0-rst # R-Car S4-8
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -0,0 +1,38 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7100 SoC Reset Controller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- starfive,jh7100-reset
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
reset-controller@11840000 {
|
||||
compatible = "starfive,jh7100-reset";
|
||||
reg = <0x11840000 0x10000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,24 +0,0 @@
|
||||
NVIDIA Tegra20 real-time clock
|
||||
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five alarm
|
||||
registers. The alarms and other interrupts may wake the system from low-power
|
||||
state.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-rtc". Otherwise,
|
||||
must contain '"nvidia,<chip>-rtc", "nvidia,tegra20-rtc"', where <chip>
|
||||
can be tegra30, tegra114, tegra124, or tegra132.
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
- interrupts : A single interrupt specifier.
|
||||
- clocks : Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
||||
Example:
|
||||
|
||||
timer {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra real-time clock
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
The Tegra RTC maintains seconds and milliseconds counters, and five
|
||||
alarm registers. The alarms and other interrupts may wake the system
|
||||
from low-power state.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra20-rtc
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra30-rtc
|
||||
- nvidia,tegra114-rtc
|
||||
- nvidia,tegra124-rtc
|
||||
- nvidia,tegra210-rtc
|
||||
- nvidia,tegra186-rtc
|
||||
- nvidia,tegra194-rtc
|
||||
- nvidia,tegra234-rtc
|
||||
- const: nvidia,tegra20-rtc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: rtc
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
timer@7000e000 {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <0 2 0x04>;
|
||||
clocks = <&tegra_car 4>;
|
||||
};
|
||||
@ -113,9 +113,10 @@ properties:
|
||||
- nvidia,tegra30-uart
|
||||
- nvidia,tegra114-uart
|
||||
- nvidia,tegra124-uart
|
||||
- nvidia,tegra210-uart
|
||||
- nvidia,tegra186-uart
|
||||
- nvidia,tegra194-uart
|
||||
- nvidia,tegra210-uart
|
||||
- nvidia,tegra234-uart
|
||||
- const: nvidia,tegra20-uart
|
||||
|
||||
reg:
|
||||
|
||||
@ -1,35 +0,0 @@
|
||||
NVIDIA Tegra Combined UART (TCU)
|
||||
|
||||
The TCU is a system for sharing a hardware UART instance among multiple
|
||||
systems within the Tegra SoC. It is implemented through a mailbox-
|
||||
based protocol where each "virtual UART" has a pair of mailboxes, one
|
||||
for transmitting and one for receiving, that is used to communicate
|
||||
with the hardware implementing the TCU.
|
||||
|
||||
Required properties:
|
||||
- name : Should be tcu
|
||||
- compatible
|
||||
Array of strings
|
||||
One of:
|
||||
- "nvidia,tegra194-tcu"
|
||||
- mbox-names:
|
||||
"rx" - Mailbox for receiving data from hardware UART
|
||||
"tx" - Mailbox for transmitting data to hardware UART
|
||||
- mboxes: Mailboxes corresponding to the mbox-names.
|
||||
|
||||
This node is a mailbox consumer. See the following files for details of
|
||||
the mailbox subsystem, and the specifiers implemented by the relevant
|
||||
provider(s):
|
||||
|
||||
- .../mailbox/mailbox.txt
|
||||
- .../mailbox/nvidia,tegra186-hsp.txt
|
||||
|
||||
Example bindings:
|
||||
-----------------
|
||||
|
||||
tcu: tcu {
|
||||
compatible = "nvidia,tegra194-tcu";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
|
||||
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
|
||||
mbox-names = "rx", "tx";
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/serial/nvidia,tegra194-tcu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Combined UART (TCU)
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description:
|
||||
The TCU is a system for sharing a hardware UART instance among multiple
|
||||
systems within the Tegra SoC. It is implemented through a mailbox-
|
||||
based protocol where each "virtual UART" has a pair of mailboxes, one
|
||||
for transmitting and one for receiving, that is used to communicate
|
||||
with the hardware implementing the TCU.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^serial(@.*)?$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra194-tcu
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra234-tcu
|
||||
- const: nvidia,tegra194-tcu
|
||||
|
||||
mbox-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
mboxes:
|
||||
description: |
|
||||
List of phandles to mailbox channels used for receiving and
|
||||
transmitting data from and to the hardware UART.
|
||||
items:
|
||||
- description: mailbox for receiving data from hardware UART
|
||||
- description: mailbox for transmitting data to hardware UART
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mbox-names
|
||||
- mboxes
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
tcu: serial {
|
||||
compatible = "nvidia,tegra194-tcu";
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM 0>,
|
||||
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM 1>;
|
||||
mbox-names = "rx", "tx";
|
||||
};
|
||||
@ -40,6 +40,11 @@ properties:
|
||||
- brcm,bcm11351-dw-apb-uart
|
||||
- brcm,bcm21664-dw-apb-uart
|
||||
- const: snps,dw-apb-uart
|
||||
- items:
|
||||
- enum:
|
||||
- starfive,jh7100-hsuart
|
||||
- starfive,jh7100-uart
|
||||
- const: snps,dw-apb-uart
|
||||
- const: snps,dw-apb-uart
|
||||
|
||||
reg:
|
||||
|
||||
@ -1,17 +0,0 @@
|
||||
Broadcom VCHIQ firmware services
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be "brcm,bcm2835-vchiq" on BCM2835, otherwise
|
||||
"brcm,bcm2836-vchiq".
|
||||
- reg: Physical base address and length of the doorbell register pair
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
Example:
|
||||
|
||||
mailbox@7e00b840 {
|
||||
compatible = "brcm,bcm2835-vchiq";
|
||||
reg = <0x7e00b840 0xf>;
|
||||
interrupts = <0 2>;
|
||||
};
|
||||
@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-vchiq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom VCHIQ firmware services
|
||||
|
||||
maintainers:
|
||||
- Nicolas Saenz Julienne <nsaenz@kernel.org>
|
||||
|
||||
description:
|
||||
The VCHIQ communication channel can be provided by BCM283x and Capri SoCs,
|
||||
to communicate with the VPU-side OS services.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: BCM2835 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm2835-vchiq
|
||||
|
||||
- description: BCM2836/BCM2837 based boards
|
||||
items:
|
||||
- enum:
|
||||
- brcm,bcm2836-vchiq
|
||||
- const: brcm,bcm2835-vchiq
|
||||
|
||||
reg:
|
||||
description: Physical base address and length of the doorbell register pair
|
||||
minItems: 1
|
||||
|
||||
interrupts:
|
||||
description: Interrupt number of the doorbell interrupt
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mailbox@7e00b840 {
|
||||
compatible = "brcm,bcm2835-vchiq";
|
||||
reg = <0x7e00b840 0xf>;
|
||||
interrupts = <0 2>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8MN DISP blk-ctrl
|
||||
|
||||
maintainers:
|
||||
- Lucas Stach <l.stach@pengutronix.de>
|
||||
|
||||
description:
|
||||
The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
|
||||
the NoC and ensuring proper power sequencing of the display and MIPI CSI
|
||||
peripherals located in the DISP domain of the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: fsl,imx8mn-disp-blk-ctrl
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
minItems: 5
|
||||
maxItems: 5
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: bus
|
||||
- const: isi
|
||||
- const: lcdif
|
||||
- const: mipi-dsi
|
||||
- const: mipi-csi
|
||||
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: disp_axi
|
||||
- const: disp_apb
|
||||
- const: disp_axi_root
|
||||
- const: disp_apb_root
|
||||
- const: lcdif-axi
|
||||
- const: lcdif-apb
|
||||
- const: lcdif-pix
|
||||
- const: dsi-pclk
|
||||
- const: dsi-ref
|
||||
- const: csi-aclk
|
||||
- const: csi-pclk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <dt-bindings/power/imx8mn-power.h>
|
||||
|
||||
disp_blk_ctl: blk_ctrl@32e28000 {
|
||||
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
|
||||
reg = <0x32e28000 0x100>;
|
||||
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
|
||||
<&pgc_dispmix>, <&pgc_mipi>,
|
||||
<&pgc_mipi>;
|
||||
power-domain-names = "bus", "isi", "lcdif", "mipi-dsi",
|
||||
"mipi-csi";
|
||||
clocks = <&clk IMX8MN_CLK_DISP_AXI>,
|
||||
<&clk IMX8MN_CLK_DISP_APB>,
|
||||
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
|
||||
<&clk IMX8MN_CLK_DSI_CORE>,
|
||||
<&clk IMX8MN_CLK_DSI_PHY_REF>,
|
||||
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
|
||||
<&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
|
||||
clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root",
|
||||
"lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
|
||||
"dsi-ref", "csi-aclk", "csi-pclk";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
@ -21,6 +21,11 @@ properties:
|
||||
enum:
|
||||
- qcom,rpmh-stats
|
||||
- qcom,rpm-stats
|
||||
# For older RPM firmware versions with fixed offset for the sleep stats
|
||||
- qcom,apq8084-rpm-stats
|
||||
- qcom,msm8226-rpm-stats
|
||||
- qcom,msm8916-rpm-stats
|
||||
- qcom,msm8974-rpm-stats
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/exynos-chipid.yaml#
|
||||
$id: http://devicetree.org/schemas/soc/samsung/exynos-chipid.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC series Chipid driver
|
||||
@ -1,7 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
|
||||
$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos SoC series Power Management Unit (PMU)
|
||||
@ -24,6 +24,7 @@ select:
|
||||
- samsung,exynos5420-pmu
|
||||
- samsung,exynos5433-pmu
|
||||
- samsung,exynos7-pmu
|
||||
- samsung,exynos850-pmu
|
||||
- samsung-s5pv210-pmu
|
||||
required:
|
||||
- compatible
|
||||
@ -41,6 +42,7 @@ properties:
|
||||
- samsung,exynos5420-pmu
|
||||
- samsung,exynos5433-pmu
|
||||
- samsung,exynos7-pmu
|
||||
- samsung,exynos850-pmu
|
||||
- samsung-s5pv210-pmu
|
||||
- const: syscon
|
||||
|
||||
159
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
Normal file
159
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
Normal file
@ -0,0 +1,159 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung's Exynos USI (Universal Serial Interface) binding
|
||||
|
||||
maintainers:
|
||||
- Sam Protsenko <semen.protsenko@linaro.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
|
||||
|
||||
description: |
|
||||
USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
|
||||
USI shares almost all internal circuits within each protocol, so only one
|
||||
protocol can be chosen at a time. USI is modeled as a node with zero or more
|
||||
child nodes, each representing a serial sub-node device. The mode setting
|
||||
selects which particular function will be used.
|
||||
|
||||
Refer to next bindings documentation for information on protocol subnodes that
|
||||
can exist under USI node:
|
||||
|
||||
[1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
|
||||
[2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
|
||||
[3] Documentation/devicetree/bindings/spi/spi-samsung.txt
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^usi@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos850-usi # for USIv2 (Exynos850, ExynosAutoV9)
|
||||
|
||||
reg: true
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-names: true
|
||||
|
||||
ranges: true
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
samsung,sysreg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should be phandle/offset pair. The phandle to System Register syscon node
|
||||
(for the same domain where this USI controller resides) and the offset
|
||||
of SW_CONF register for this USI controller.
|
||||
|
||||
samsung,mode:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Selects USI function (which serial protocol to use). Refer to
|
||||
<include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
|
||||
|
||||
samsung,clkreq-on:
|
||||
type: boolean
|
||||
description:
|
||||
Enable this property if underlying protocol requires the clock to be
|
||||
continuously provided without automatic gating. As suggested by SoC
|
||||
manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
|
||||
multi-master mode. Usually this property is needed if USI mode is set
|
||||
to "UART".
|
||||
|
||||
This property is optional.
|
||||
|
||||
patternProperties:
|
||||
# All other properties should be child nodes
|
||||
"^(serial|spi|i2c)@[0-9a-f]+$":
|
||||
type: object
|
||||
description: Child node describing underlying USI serial protocol
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- ranges
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- samsung,sysreg
|
||||
- samsung,mode
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos850-usi
|
||||
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Bus (APB) clock
|
||||
- description: Operating clock for UART/SPI/I2C protocol
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: ipclk
|
||||
|
||||
required:
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
else:
|
||||
properties:
|
||||
reg: false
|
||||
clocks: false
|
||||
clock-names: false
|
||||
samsung,clkreq-on: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/samsung,exynos-usi.h>
|
||||
|
||||
usi0: usi@138200c0 {
|
||||
compatible = "samsung,exynos850-usi";
|
||||
reg = <0x138200c0 0x20>;
|
||||
samsung,sysreg = <&sysreg_peri 0x1010>;
|
||||
samsung,mode = <USI_V2_UART>;
|
||||
samsung,clkreq-on; /* needed for UART mode */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clocks = <&cmu_peri 32>, <&cmu_peri 31>;
|
||||
clock-names = "pclk", "ipclk";
|
||||
|
||||
serial_0: serial@13820000 {
|
||||
compatible = "samsung,exynos850-uart";
|
||||
reg = <0x13820000 0xc0>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_peri 32>, <&cmu_peri 31>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsi2c_0: i2c@13820000 {
|
||||
compatible = "samsung,exynosautov9-hsi2c";
|
||||
reg = <0x13820000 0xc0>;
|
||||
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&cmu_peri 31>, <&cmu_peri 32>;
|
||||
clock-names = "hsi2c", "hsi2c_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@ -29,6 +29,7 @@ properties:
|
||||
- ti,am654-ospi
|
||||
- intel,lgm-qspi
|
||||
- xlnx,versal-ospi-1.0
|
||||
- intel,socfpga-qspi
|
||||
- const: cdns,qspi-nor
|
||||
- const: cdns,qspi-nor
|
||||
|
||||
|
||||
@ -31,6 +31,9 @@ properties:
|
||||
- amlogic,meson-gxbb-sram
|
||||
- arm,juno-sram-ns
|
||||
- atmel,sama5d2-securam
|
||||
- nvidia,tegra186-sysram
|
||||
- nvidia,tegra194-sysram
|
||||
- nvidia,tegra234-sysram
|
||||
- qcom,rpm-msg-ram
|
||||
- rockchip,rk3288-pmu-sram
|
||||
|
||||
|
||||
@ -1,33 +0,0 @@
|
||||
NVIDIA Tegra186 BPMP thermal sensor
|
||||
|
||||
In Tegra186, the BPMP (Boot and Power Management Processor) implements an
|
||||
interface that is used to read system temperatures, including CPU cluster
|
||||
and GPU temperatures. This binding describes the thermal sensor that is
|
||||
exposed by BPMP.
|
||||
|
||||
The BPMP thermal node must be located directly inside the main BPMP node. See
|
||||
../firmware/nvidia,tegra186-bpmp.txt for details of the BPMP binding.
|
||||
|
||||
This node represents a thermal sensor. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for details of the
|
||||
core thermal binding.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Array of strings.
|
||||
One of:
|
||||
- "nvidia,tegra186-bpmp-thermal"
|
||||
- "nvidia,tegra194-bpmp-thermal"
|
||||
- #thermal-sensor-cells: Cell for sensor index.
|
||||
Single-cell integer.
|
||||
Must be <1>.
|
||||
|
||||
Example:
|
||||
|
||||
bpmp {
|
||||
...
|
||||
|
||||
bpmp_thermal: thermal {
|
||||
compatible = "nvidia,tegra186-bpmp-thermal";
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,42 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/thermal/nvidia,tegra186-bpmp-thermal.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 (and later) BPMP thermal sensor
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
In Tegra186, the BPMP (Boot and Power Management Processor) implements
|
||||
an interface that is used to read system temperatures, including CPU
|
||||
cluster and GPU temperatures. This binding describes the thermal
|
||||
sensor that is exposed by BPMP.
|
||||
|
||||
The BPMP thermal node must be located directly inside the main BPMP
|
||||
node. See ../firmware/nvidia,tegra186-bpmp.yaml for details of the
|
||||
BPMP binding.
|
||||
|
||||
This node represents a thermal sensor. See
|
||||
|
||||
Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
|
||||
|
||||
for details of the core thermal binding.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra186-bpmp-thermal
|
||||
- nvidia,tegra194-bpmp-thermal
|
||||
|
||||
'#thermal-sensor-cells':
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of cells needed in the phandle specifier to
|
||||
identify a given sensor. Must be 1 and the single cell specifies
|
||||
the sensor index.
|
||||
const: 1
|
||||
|
||||
additionalProperties: false
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-clint
|
||||
- starfive,jh7100-clint
|
||||
- canaan,k210-clint
|
||||
- const: sifive,clint0
|
||||
|
||||
|
||||
@ -59,6 +59,19 @@ properties:
|
||||
- const: fs_src
|
||||
- const: hs_src
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: memory read client
|
||||
- description: memory write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: XUSBB(device) power-domain
|
||||
|
||||
@ -187,6 +187,8 @@ patternProperties:
|
||||
description: Shanghai Broadmobi Communication Technology Co.,Ltd.
|
||||
"^brcm,.*":
|
||||
description: Broadcom Corporation
|
||||
"^bsh,.*":
|
||||
description: BSH Hausgeraete GmbH
|
||||
"^buffalo,.*":
|
||||
description: Buffalo, Inc.
|
||||
"^bur,.*":
|
||||
@ -593,6 +595,8 @@ patternProperties:
|
||||
description: JetHome (IP Sokolov P.A.)
|
||||
"^jianda,.*":
|
||||
description: Jiandangjing Technology Co., Ltd.
|
||||
"^joz,.*":
|
||||
description: JOZ BV
|
||||
"^kam,.*":
|
||||
description: Kamstrup A/S
|
||||
"^karo,.*":
|
||||
@ -1318,6 +1322,8 @@ patternProperties:
|
||||
description: Wiligear, Ltd.
|
||||
"^winbond,.*":
|
||||
description: Winbond Electronics corp.
|
||||
"^winlink,.*":
|
||||
description: WinLink Co., Ltd
|
||||
"^winstar,.*":
|
||||
description: Winstar Display Corp.
|
||||
"^wits,.*":
|
||||
@ -1350,6 +1356,8 @@ patternProperties:
|
||||
description: Shenzhen Xunlong Software CO.,Limited
|
||||
"^xylon,.*":
|
||||
description: Xylon
|
||||
"^yadro,.*":
|
||||
description: YADRO
|
||||
"^yamaha,.*":
|
||||
description: Yamaha Corporation
|
||||
"^yes-optoelectronics,.*":
|
||||
|
||||
52
Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
Normal file
52
Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
Normal file
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/watchdog/apple,wdt.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoC Watchdog
|
||||
|
||||
allOf:
|
||||
- $ref: "watchdog.yaml#"
|
||||
|
||||
maintainers:
|
||||
- Sven Peter <sven@svenpeter.dev>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,t8103-wdt
|
||||
- apple,t6000-wdt
|
||||
- const: apple,wdt
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/apple-aic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
wdt: watchdog@50000000 {
|
||||
compatible = "apple,t8103-wdt", "apple,wdt";
|
||||
reg = <0x50000000 0x4000>;
|
||||
clocks = <&clk>;
|
||||
interrupts = <AIC_IRQ 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -181,5 +181,24 @@ You should see something like this in dmesg::
|
||||
[22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
|
||||
[22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0)
|
||||
|
||||
Special notes for injection into SGX enclaves:
|
||||
|
||||
There may be a separate BIOS setup option to enable SGX injection.
|
||||
|
||||
The injection process consists of setting some special memory controller
|
||||
trigger that will inject the error on the next write to the target
|
||||
address. But the h/w prevents any software outside of an SGX enclave
|
||||
from accessing enclave pages (even BIOS SMM mode).
|
||||
|
||||
The following sequence can be used:
|
||||
1) Determine physical address of enclave page
|
||||
2) Use "notrigger=1" mode to inject (this will setup
|
||||
the injection address, but will not actually inject)
|
||||
3) Enter the enclave
|
||||
4) Store data to the virtual address matching physical address from step 1
|
||||
5) Execute CLFLUSH for that virtual address
|
||||
6) Spin delay for 250ms
|
||||
7) Read from the virtual address. This will trigger the error
|
||||
|
||||
For more information about EINJ, please refer to ACPI specification
|
||||
version 4.0, section 17.5 and ACPI 5.0, section 18.6.
|
||||
|
||||
@ -1950,6 +1950,14 @@ There are some more advanced barrier functions:
|
||||
For load from persistent memory, existing read memory barriers are sufficient
|
||||
to ensure read ordering.
|
||||
|
||||
(*) io_stop_wc();
|
||||
|
||||
For memory accesses with write-combining attributes (e.g. those returned
|
||||
by ioremap_wc(), the CPU may wait for prior accesses to be merged with
|
||||
subsequent ones. io_stop_wc() can be used to prevent the merging of
|
||||
write-combining memory accesses before this macro with those after it when
|
||||
such wait has performance implications.
|
||||
|
||||
===============================
|
||||
IMPLICIT KERNEL MEMORY BARRIERS
|
||||
===============================
|
||||
|
||||
@ -184,6 +184,36 @@ order to support device enumeration. In other words, OP-TEE driver invokes this
|
||||
application to retrieve a list of Trusted Applications which can be registered
|
||||
as devices on the TEE bus.
|
||||
|
||||
OP-TEE notifications
|
||||
--------------------
|
||||
|
||||
There are two kinds of notifications that secure world can use to make
|
||||
normal world aware of some event.
|
||||
|
||||
1. Synchronous notifications delivered with ``OPTEE_RPC_CMD_NOTIFICATION``
|
||||
using the ``OPTEE_RPC_NOTIFICATION_SEND`` parameter.
|
||||
2. Asynchronous notifications delivered with a combination of a non-secure
|
||||
edge-triggered interrupt and a fast call from the non-secure interrupt
|
||||
handler.
|
||||
|
||||
Synchronous notifications are limited by depending on RPC for delivery,
|
||||
this is only usable when secure world is entered with a yielding call via
|
||||
``OPTEE_SMC_CALL_WITH_ARG``. This excludes such notifications from secure
|
||||
world interrupt handlers.
|
||||
|
||||
An asynchronous notification is delivered via a non-secure edge-triggered
|
||||
interrupt to an interrupt handler registered in the OP-TEE driver. The
|
||||
actual notification value are retrieved with the fast call
|
||||
``OPTEE_SMC_GET_ASYNC_NOTIF_VALUE``. Note that one interrupt can represent
|
||||
multiple notifications.
|
||||
|
||||
One notification value ``OPTEE_SMC_ASYNC_NOTIF_VALUE_DO_BOTTOM_HALF`` has a
|
||||
special meaning. When this value is received it means that normal world is
|
||||
supposed to make a yielding call ``OPTEE_MSG_CMD_DO_BOTTOM_HALF``. This
|
||||
call is done from the thread assisting the interrupt handler. This is a
|
||||
building block for OP-TEE OS in secure world to implement the top half and
|
||||
bottom half style of device drivers.
|
||||
|
||||
AMD-TEE driver
|
||||
==============
|
||||
|
||||
|
||||
@ -10,7 +10,7 @@ Overview
|
||||
Software Guard eXtensions (SGX) hardware enables for user space applications
|
||||
to set aside private memory regions of code and data:
|
||||
|
||||
* Privileged (ring-0) ENCLS functions orchestrate the construction of the.
|
||||
* Privileged (ring-0) ENCLS functions orchestrate the construction of the
|
||||
regions.
|
||||
* Unprivileged (ring-3) ENCLU functions allow an application to enter and
|
||||
execute inside the regions.
|
||||
@ -91,7 +91,7 @@ In addition to the traditional compiler and linker build process, SGX has a
|
||||
separate enclave “build” process. Enclaves must be built before they can be
|
||||
executed (entered). The first step in building an enclave is opening the
|
||||
**/dev/sgx_enclave** device. Since enclave memory is protected from direct
|
||||
access, special privileged instructions are Then used to copy data into enclave
|
||||
access, special privileged instructions are then used to copy data into enclave
|
||||
pages and establish enclave page permissions.
|
||||
|
||||
.. kernel-doc:: arch/x86/kernel/cpu/sgx/ioctl.c
|
||||
@ -126,13 +126,13 @@ the need to juggle signal handlers.
|
||||
ksgxd
|
||||
=====
|
||||
|
||||
SGX support includes a kernel thread called *ksgxwapd*.
|
||||
SGX support includes a kernel thread called *ksgxd*.
|
||||
|
||||
EPC sanitization
|
||||
----------------
|
||||
|
||||
ksgxd is started when SGX initializes. Enclave memory is typically ready
|
||||
For use when the processor powers on or resets. However, if SGX has been in
|
||||
for use when the processor powers on or resets. However, if SGX has been in
|
||||
use since the reset, enclave pages may be in an inconsistent state. This might
|
||||
occur after a crash and kexec() cycle, for instance. At boot, ksgxd
|
||||
reinitializes all enclave pages so that they can be allocated and re-used.
|
||||
@ -147,7 +147,7 @@ Page reclaimer
|
||||
|
||||
Similar to the core kswapd, ksgxd, is responsible for managing the
|
||||
overcommitment of enclave memory. If the system runs out of enclave memory,
|
||||
*ksgxwapd* “swaps” enclave memory to normal memory.
|
||||
*ksgxd* “swaps” enclave memory to normal memory.
|
||||
|
||||
Launch Control
|
||||
==============
|
||||
@ -156,7 +156,7 @@ SGX provides a launch control mechanism. After all enclave pages have been
|
||||
copied, kernel executes EINIT function, which initializes the enclave. Only after
|
||||
this the CPU can execute inside the enclave.
|
||||
|
||||
ENIT function takes an RSA-3072 signature of the enclave measurement. The function
|
||||
EINIT function takes an RSA-3072 signature of the enclave measurement. The function
|
||||
checks that the measurement is correct and signature is signed with the key
|
||||
hashed to the four **IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}** MSRs representing the
|
||||
SHA256 of a public key.
|
||||
@ -184,7 +184,7 @@ CPUs starting from Icelake use Total Memory Encryption (TME) in the place of
|
||||
MEE. TME-based SGX implementations do not have an integrity Merkle tree, which
|
||||
means integrity and replay-attacks are not mitigated. B, it includes
|
||||
additional changes to prevent cipher text from being returned and SW memory
|
||||
aliases from being Created.
|
||||
aliases from being created.
|
||||
|
||||
DMA to enclave memory is blocked by range registers on both MEE and TME systems
|
||||
(SDM section 41.10).
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user