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[ARM] pxa: add basic support for Littleton (PXA3xx Form Factor Platform)
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
eric miao
Russell King
parent
e5c271ec3b
commit
e1d9b95325
@ -107,6 +107,11 @@ config MACH_ZYLONITE
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bool "PXA3xx Development Platform"
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select PXA3xx
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config MACH_LITTLETON
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bool "PXA3xx Form Factor Platform (aka Littleton)"
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select PXA3xx
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select PXA_SSP
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config MACH_ARMCORE
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bool "CompuLab CM-X270 modules"
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select PXA27x
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@ -30,6 +30,7 @@ ifeq ($(CONFIG_MACH_ZYLONITE),y)
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obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
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obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
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endif
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obj-$(CONFIG_MACH_LITTLETON) += littleton.o
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obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
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325
arch/arm/mach-pxa/littleton.c
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325
arch/arm/mach-pxa/littleton.c
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@ -0,0 +1,325 @@
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/*
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* linux/arch/arm/mach-pxa/littleton.c
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*
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* Support for the Marvell Littleton Development Platform.
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*
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* Author: Jason Chagas (largely modified code)
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* Created: Nov 20, 2006
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* Copyright: (C) Copyright 2006 Marvell International Ltd.
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*
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* 2007-11-22 modified to align with latest kernel
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* eric miao <eric.miao@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <asm/mach-types.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/mfp-pxa300.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pxafb.h>
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#include <asm/arch/ssp.h>
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#include <asm/arch/littleton.h>
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#include "generic.h"
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#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
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/* Littleton MFP configurations */
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static mfp_cfg_t littleton_mfp_cfg[] __initdata = {
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/* LCD */
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GPIO54_LCD_LDD_0,
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GPIO55_LCD_LDD_1,
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GPIO56_LCD_LDD_2,
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GPIO57_LCD_LDD_3,
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GPIO58_LCD_LDD_4,
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GPIO59_LCD_LDD_5,
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GPIO60_LCD_LDD_6,
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GPIO61_LCD_LDD_7,
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GPIO62_LCD_LDD_8,
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GPIO63_LCD_LDD_9,
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GPIO64_LCD_LDD_10,
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GPIO65_LCD_LDD_11,
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GPIO66_LCD_LDD_12,
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GPIO67_LCD_LDD_13,
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GPIO68_LCD_LDD_14,
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GPIO69_LCD_LDD_15,
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GPIO70_LCD_LDD_16,
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GPIO71_LCD_LDD_17,
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GPIO72_LCD_FCLK,
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GPIO73_LCD_LCLK,
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GPIO74_LCD_PCLK,
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GPIO75_LCD_BIAS,
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/* SSP2 */
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GPIO25_SSP2_SCLK,
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GPIO17_SSP2_FRM,
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GPIO27_SSP2_TXD,
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/* Debug Ethernet */
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GPIO90_GPIO,
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};
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = (LITTLETON_ETH_PHYS + 0x300),
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.end = (LITTLETON_ETH_PHYS + 0xfffff),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
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.end = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULES)
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/* use bit 30, 31 as the indicator of command parameter number */
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#define CMD0(x) ((0x00000000) | ((x) << 9))
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#define CMD1(x, x1) ((0x40000000) | ((x) << 9) | 0x100 | (x1))
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#define CMD2(x, x1, x2) ((0x80000000) | ((x) << 18) | 0x20000 |\
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((x1) << 9) | 0x100 | (x2))
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static uint32_t lcd_panel_reset[] = {
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CMD0(0x1), /* reset */
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CMD0(0x0), /* nop */
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CMD0(0x0), /* nop */
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CMD0(0x0), /* nop */
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};
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static uint32_t lcd_panel_on[] = {
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CMD0(0x29), /* Display ON */
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CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
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CMD0(0x11), /* Sleep out */
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CMD1(0xB0, 0x16), /* Wake */
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};
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static uint32_t lcd_panel_off[] = {
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CMD0(0x28), /* Display OFF */
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CMD2(0xB8, 0x80, 0x02), /* Output Control */
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CMD0(0x10), /* Sleep in */
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CMD1(0xB0, 0x00), /* Deep stand by in */
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};
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static uint32_t lcd_vga_pass_through[] = {
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CMD1(0xB0, 0x16),
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CMD1(0xBC, 0x80),
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CMD1(0xE1, 0x00),
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CMD1(0x36, 0x50),
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CMD1(0x3B, 0x00),
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};
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static uint32_t lcd_qvga_pass_through[] = {
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CMD1(0xB0, 0x16),
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CMD1(0xBC, 0x81),
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CMD1(0xE1, 0x00),
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CMD1(0x36, 0x50),
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CMD1(0x3B, 0x22),
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};
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static uint32_t lcd_vga_transfer[] = {
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CMD1(0xcf, 0x02), /* Blanking period control (1) */
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CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
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CMD1(0xd1, 0x01), /* CKV timing control on/off */
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CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
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CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
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CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
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CMD1(0xd5, 0x14), /* ASW timing control (2) */
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CMD0(0x21), /* Invert for normally black display */
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CMD0(0x29), /* Display on */
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};
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static uint32_t lcd_qvga_transfer[] = {
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CMD1(0xd6, 0x02), /* Blanking period control (1) */
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CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
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CMD1(0xd8, 0x01), /* CKV timing control on/off */
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CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
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CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
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CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
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CMD1(0xe0, 0x0a), /* ASW timing control (2) */
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CMD0(0x21), /* Invert for normally black display */
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CMD0(0x29), /* Display on */
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};
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static uint32_t lcd_panel_config[] = {
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CMD2(0xb8, 0xff, 0xf9), /* Output control */
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CMD0(0x11), /* sleep out */
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CMD1(0xba, 0x01), /* Display mode (1) */
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CMD1(0xbb, 0x00), /* Display mode (2) */
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CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
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CMD1(0xbf, 0x10), /* Drive system change control */
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CMD1(0xb1, 0x56), /* Booster operation setup */
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CMD1(0xb2, 0x33), /* Booster mode setup */
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CMD1(0xb3, 0x11), /* Booster frequency setup */
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CMD1(0xb4, 0x02), /* Op amp/system clock */
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CMD1(0xb5, 0x35), /* VCS voltage */
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CMD1(0xb6, 0x40), /* VCOM voltage */
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CMD1(0xb7, 0x03), /* External display signal */
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CMD1(0xbd, 0x00), /* ASW slew rate */
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CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
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CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
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CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
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CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
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CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
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CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
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CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
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CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
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CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
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CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
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CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
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CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
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CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
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};
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static void ssp_reconfig(struct ssp_dev *dev, int nparam)
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{
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static int last_nparam = -1;
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/* check if it is necessary to re-config SSP */
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if (nparam == last_nparam)
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return;
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ssp_disable(dev);
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ssp_config(dev, (nparam == 2) ? 0x0010058a : 0x00100581, 0x18, 0, 0);
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last_nparam = nparam;
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}
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static void ssp_send_cmd(uint32_t *cmd, int num)
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{
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static int ssp_initialized;
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static struct ssp_dev ssp2;
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int i;
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if (!ssp_initialized) {
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ssp_init(&ssp2, 2, SSP_NO_IRQ);
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ssp_initialized = 1;
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}
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clk_enable(ssp2.ssp->clk);
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for (i = 0; i < num; i++, cmd++) {
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ssp_reconfig(&ssp2, (*cmd >> 30) & 0x3);
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ssp_write_word(&ssp2, *cmd & 0x3fffffff);
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/* FIXME: ssp_flush() is mandatory here to work */
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ssp_flush(&ssp2);
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}
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clk_disable(ssp2.ssp->clk);
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}
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static void littleton_lcd_power(int on, struct fb_var_screeninfo *var)
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{
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if (on) {
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_on));
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_reset));
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if (var->xres > 240) {
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/* VGA */
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_pass_through));
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_vga_transfer));
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} else {
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/* QVGA */
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_pass_through));
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_config));
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_qvga_transfer));
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}
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} else
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ssp_send_cmd(ARRAY_AND_SIZE(lcd_panel_off));
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}
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static struct pxafb_mode_info tpo_tdo24mtea1_modes[] = {
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[0] = {
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/* VGA */
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.pixclock = 38250,
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.xres = 480,
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.yres = 640,
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.bpp = 16,
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.hsync_len = 8,
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.left_margin = 8,
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.right_margin = 24,
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.vsync_len = 2,
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.upper_margin = 2,
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.lower_margin = 4,
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.sync = 0,
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},
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[1] = {
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/* QVGA */
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.pixclock = 153000,
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.xres = 240,
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.yres = 320,
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.bpp = 16,
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.hsync_len = 8,
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.left_margin = 8,
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.right_margin = 88,
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.vsync_len = 2,
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.upper_margin = 2,
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.lower_margin = 2,
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.sync = 0,
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},
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};
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static struct pxafb_mach_info littleton_lcd_info = {
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.modes = tpo_tdo24mtea1_modes,
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.num_modes = 2,
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.lccr0 = LCCR0_Act,
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.lccr3 = LCCR3_HSP | LCCR3_VSP,
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.pxafb_lcd_power = littleton_lcd_power,
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};
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static void littleton_init_lcd(void)
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{
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set_pxa_fb_info(&littleton_lcd_info);
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}
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#else
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static inline void littleton_init_lcd(void) {};
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#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULES */
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static void __init littleton_init(void)
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{
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/* initialize MFP configurations */
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pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg));
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/*
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* Note: we depend bootloader set the correct
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* value to MSC register for SMC91x.
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*/
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platform_device_register(&smc91x_device);
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littleton_init_lcd();
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}
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MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
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.phys_io = 0x40000000,
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.boot_params = 0xa0000100,
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.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
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.map_io = pxa_map_io,
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.init_irq = pxa3xx_init_irq,
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.timer = &pxa_timer,
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.init_machine = littleton_init,
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MACHINE_END
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6
include/asm-arm/arch-pxa/littleton.h
Normal file
6
include/asm-arm/arch-pxa/littleton.h
Normal file
@ -0,0 +1,6 @@
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#ifndef __ASM_ARCH_ZYLONITE_H
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#define __ASM_ARCH_ZYLONITE_H
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#define LITTLETON_ETH_PHYS 0x30000000
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#endif /* __ASM_ARCH_ZYLONITE_H */
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