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This series adds basic TI DRA7xx PRCM and hwmod support.

Browse Source 
Basic test logs are available here:
 
 http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/
 
 Note that DRA7xx could not be tested locally, since I don't have a board.
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Merge tag 'for-v3.12/dra7xx' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.12/soc

This series adds basic TI DRA7xx PRCM and hwmod support.

Basic test logs are available here:

http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/

Note that DRA7xx could not be tested locally, since I don't have a board.
This commit is contained in:
Tony Lindgren 2013-08-26 02:53:05 -07:00
commit e3e1970f89
17 changed files with 5606 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-omap2/Makefile
View File

@ -63,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
# Pin multiplexing
obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@ -148,6 +149,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
@ -166,6 +168,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@ -209,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o

1
arch/arm/mach-omap2/board-generic.c
View File

@ -238,5 +238,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
.init_machine = omap_generic_init,
.init_time = omap5_realtime_timer_init,
.dt_compat = dra7xx_boards_compat,
.restart = omap44xx_restart,
MACHINE_END
#endif

1
arch/arm/mach-omap2/clockdomain.h
View File

@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
extern void __init dra7xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);

740
arch/arm/mach-omap2/clockdomains7xx_data.c Normal file
View File

@ -0,0 +1,740 @@
/*
* DRA7xx Clock domains framework
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Generated by code originally written by:
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include "clockdomain.h"
#include "cm1_7xx.h"
#include "cm2_7xx.h"
#include "cm-regbits-7xx.h"
#include "prm7xx.h"
#include "prcm44xx.h"
#include "prcm_mpu7xx.h"
/* Static Dependencies for DRA7xx Clock Domains */
static struct clkdm_dep cam_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ NULL },
};
static struct clkdm_dep dma_wkup_sleep_deps[] = {
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
{ .clkdm_name = "atl_clkdm" },
{ .clkdm_name = "cam_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
{ .clkdm_name = "atl_clkdm" },
{ .clkdm_name = "cam_clkdm" },
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep dss_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep eve1_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep eve2_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep eve3_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep eve4_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep gmac_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ NULL },
};
static struct clkdm_dep gpu_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ NULL },
};
static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
{ .clkdm_name = "atl_clkdm" },
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
{ .clkdm_name = "atl_clkdm" },
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep iva_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ NULL },
};
static struct clkdm_dep l3init_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ NULL },
};
static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ NULL },
};
static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{ .clkdm_name = "cam_clkdm" },
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "ipu2_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l3main1_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "pcie_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ .clkdm_name = "wkupaon_clkdm" },
{ NULL },
};
static struct clkdm_dep pcie_wkup_sleep_deps[] = {
{ .clkdm_name = "atl_clkdm" },
{ .clkdm_name = "cam_clkdm" },
{ .clkdm_name = "dsp1_clkdm" },
{ .clkdm_name = "dsp2_clkdm" },
{ .clkdm_name = "dss_clkdm" },
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "eve1_clkdm" },
{ .clkdm_name = "eve2_clkdm" },
{ .clkdm_name = "eve3_clkdm" },
{ .clkdm_name = "eve4_clkdm" },
{ .clkdm_name = "gmac_clkdm" },
{ .clkdm_name = "gpu_clkdm" },
{ .clkdm_name = "ipu_clkdm" },
{ .clkdm_name = "ipu1_clkdm" },
{ .clkdm_name = "iva_clkdm" },
{ .clkdm_name = "l3init_clkdm" },
{ .clkdm_name = "l4cfg_clkdm" },
{ .clkdm_name = "l4per_clkdm" },
{ .clkdm_name = "l4per2_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ .clkdm_name = "l4sec_clkdm" },
{ .clkdm_name = "vpe_clkdm" },
{ NULL },
};
static struct clkdm_dep vpe_wkup_sleep_deps[] = {
{ .clkdm_name = "emif_clkdm" },
{ .clkdm_name = "l4per3_clkdm" },
{ NULL },
};
static struct clockdomain l4per3_7xx_clkdm = {
.name = "l4per3_clkdm",
.pwrdm = { .name = "l4per_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L4PER_INST,
.clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
.dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4per2_7xx_clkdm = {
.name = "l4per2_clkdm",
.pwrdm = { .name = "l4per_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L4PER_INST,
.clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
.dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
.wkdep_srcs = l4per2_wkup_sleep_deps,
.sleepdep_srcs = l4per2_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain mpu0_7xx_clkdm = {
.name = "mpu0_clkdm",
.pwrdm = { .name = "cpu0_pwrdm" },
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
.clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain iva_7xx_clkdm = {
.name = "iva_clkdm",
.pwrdm = { .name = "iva_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_IVA_INST,
.clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
.dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
.wkdep_srcs = iva_wkup_sleep_deps,
.sleepdep_srcs = iva_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain coreaon_7xx_clkdm = {
.name = "coreaon_clkdm",
.pwrdm = { .name = "coreaon_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_COREAON_INST,
.clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain ipu1_7xx_clkdm = {
.name = "ipu1_clkdm",
.pwrdm = { .name = "ipu_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
.dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
.wkdep_srcs = ipu1_wkup_sleep_deps,
.sleepdep_srcs = ipu1_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain ipu2_7xx_clkdm = {
.name = "ipu2_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
.dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
.wkdep_srcs = ipu2_wkup_sleep_deps,
.sleepdep_srcs = ipu2_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l3init_7xx_clkdm = {
.name = "l3init_clkdm",
.pwrdm = { .name = "l3init_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
.clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
.dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
.wkdep_srcs = l3init_wkup_sleep_deps,
.sleepdep_srcs = l3init_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4sec_7xx_clkdm = {
.name = "l4sec_clkdm",
.pwrdm = { .name = "l4per_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L4PER_INST,
.clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
.dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
.wkdep_srcs = l4sec_wkup_sleep_deps,
.sleepdep_srcs = l4sec_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l3main1_7xx_clkdm = {
.name = "l3main1_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
.dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain vpe_7xx_clkdm = {
.name = "vpe_clkdm",
.pwrdm = { .name = "vpe_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
.dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
.wkdep_srcs = vpe_wkup_sleep_deps,
.sleepdep_srcs = vpe_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain mpu_7xx_clkdm = {
.name = "mpu_clkdm",
.pwrdm = { .name = "mpu_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
.wkdep_srcs = mpu_wkup_sleep_deps,
.sleepdep_srcs = mpu_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain custefuse_7xx_clkdm = {
.name = "custefuse_clkdm",
.pwrdm = { .name = "custefuse_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain ipu_7xx_clkdm = {
.name = "ipu_clkdm",
.pwrdm = { .name = "ipu_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
.dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain mpu1_7xx_clkdm = {
.name = "mpu1_clkdm",
.pwrdm = { .name = "cpu1_pwrdm" },
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
.clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain gmac_7xx_clkdm = {
.name = "gmac_clkdm",
.pwrdm = { .name = "l3init_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
.clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
.dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
.wkdep_srcs = gmac_wkup_sleep_deps,
.sleepdep_srcs = gmac_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4cfg_7xx_clkdm = {
.name = "l4cfg_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
.dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP,
};
static struct clockdomain dma_7xx_clkdm = {
.name = "dma_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
.wkdep_srcs = dma_wkup_sleep_deps,
.sleepdep_srcs = dma_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain rtc_7xx_clkdm = {
.name = "rtc_clkdm",
.pwrdm = { .name = "rtc_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain pcie_7xx_clkdm = {
.name = "pcie_clkdm",
.pwrdm = { .name = "l3init_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
.clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
.dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
.wkdep_srcs = pcie_wkup_sleep_deps,
.sleepdep_srcs = pcie_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain atl_7xx_clkdm = {
.name = "atl_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
.dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain l3instr_7xx_clkdm = {
.name = "l3instr_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
};
static struct clockdomain dss_7xx_clkdm = {
.name = "dss_clkdm",
.pwrdm = { .name = "dss_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_DSS_INST,
.clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
.dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
.wkdep_srcs = dss_wkup_sleep_deps,
.sleepdep_srcs = dss_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain emif_7xx_clkdm = {
.name = "emif_clkdm",
.pwrdm = { .name = "core_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CORE_INST,
.clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
.dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain emu_7xx_clkdm = {
.name = "emu_clkdm",
.pwrdm = { .name = "emu_pwrdm" },
.prcm_partition = DRA7XX_PRM_PARTITION,
.cm_inst = DRA7XX_PRM_EMU_CM_INST,
.clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain dsp2_7xx_clkdm = {
.name = "dsp2_clkdm",
.pwrdm = { .name = "dsp2_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
.dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
.wkdep_srcs = dsp2_wkup_sleep_deps,
.sleepdep_srcs = dsp2_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain dsp1_7xx_clkdm = {
.name = "dsp1_clkdm",
.pwrdm = { .name = "dsp1_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
.dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
.wkdep_srcs = dsp1_wkup_sleep_deps,
.sleepdep_srcs = dsp1_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain cam_7xx_clkdm = {
.name = "cam_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_CAM_INST,
.clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
.dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
.wkdep_srcs = cam_wkup_sleep_deps,
.sleepdep_srcs = cam_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain l4per_7xx_clkdm = {
.name = "l4per_clkdm",
.pwrdm = { .name = "l4per_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_L4PER_INST,
.clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
.dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain gpu_7xx_clkdm = {
.name = "gpu_clkdm",
.pwrdm = { .name = "gpu_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_PARTITION,
.cm_inst = DRA7XX_CM_CORE_GPU_INST,
.clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
.dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
.wkdep_srcs = gpu_wkup_sleep_deps,
.sleepdep_srcs = gpu_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain eve4_7xx_clkdm = {
.name = "eve4_clkdm",
.pwrdm = { .name = "eve4_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
.dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
.wkdep_srcs = eve4_wkup_sleep_deps,
.sleepdep_srcs = eve4_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain eve2_7xx_clkdm = {
.name = "eve2_clkdm",
.pwrdm = { .name = "eve2_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
.dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
.wkdep_srcs = eve2_wkup_sleep_deps,
.sleepdep_srcs = eve2_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain eve3_7xx_clkdm = {
.name = "eve3_clkdm",
.pwrdm = { .name = "eve3_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
.dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
.wkdep_srcs = eve3_wkup_sleep_deps,
.sleepdep_srcs = eve3_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
static struct clockdomain wkupaon_7xx_clkdm = {
.name = "wkupaon_clkdm",
.pwrdm = { .name = "wkupaon_pwrdm" },
.prcm_partition = DRA7XX_PRM_PARTITION,
.cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
.clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
.dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
};
static struct clockdomain eve1_7xx_clkdm = {
.name = "eve1_clkdm",
.pwrdm = { .name = "eve1_pwrdm" },
.prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
.cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
.clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
.dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
.wkdep_srcs = eve1_wkup_sleep_deps,
.sleepdep_srcs = eve1_wkup_sleep_deps,
.flags = CLKDM_CAN_HWSUP_SWSUP,
};
/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_dra7xx[] __initdata = {
&l4per3_7xx_clkdm,
&l4per2_7xx_clkdm,
&mpu0_7xx_clkdm,
&iva_7xx_clkdm,
&coreaon_7xx_clkdm,
&ipu1_7xx_clkdm,
&ipu2_7xx_clkdm,
&l3init_7xx_clkdm,
&l4sec_7xx_clkdm,
&l3main1_7xx_clkdm,
&vpe_7xx_clkdm,
&mpu_7xx_clkdm,
&custefuse_7xx_clkdm,
&ipu_7xx_clkdm,
&mpu1_7xx_clkdm,
&gmac_7xx_clkdm,
&l4cfg_7xx_clkdm,
&dma_7xx_clkdm,
&rtc_7xx_clkdm,
&pcie_7xx_clkdm,
&atl_7xx_clkdm,
&l3instr_7xx_clkdm,
&dss_7xx_clkdm,
&emif_7xx_clkdm,
&emu_7xx_clkdm,
&dsp2_7xx_clkdm,
&dsp1_7xx_clkdm,
&cam_7xx_clkdm,
&l4per_7xx_clkdm,
&gpu_7xx_clkdm,
&eve4_7xx_clkdm,
&eve2_7xx_clkdm,
&eve3_7xx_clkdm,
&wkupaon_7xx_clkdm,
&eve1_7xx_clkdm,
NULL
};
void __init dra7xx_clockdomains_init(void)
{
clkdm_register_platform_funcs(&omap4_clkdm_operations);
clkdm_register_clkdms(clockdomains_dra7xx);
clkdm_complete_init();
}

51
arch/arm/mach-omap2/cm-regbits-7xx.h Normal file
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/*
* DRA7xx Clock Management register bits
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
#define DRA7XX_ATL_STATDEP_SHIFT 30
#define DRA7XX_CAM_STATDEP_SHIFT 9
#define DRA7XX_DSP1_STATDEP_SHIFT 1
#define DRA7XX_DSP2_STATDEP_SHIFT 18
#define DRA7XX_DSS_STATDEP_SHIFT 8
#define DRA7XX_EMIF_STATDEP_SHIFT 4
#define DRA7XX_EVE1_STATDEP_SHIFT 19
#define DRA7XX_EVE2_STATDEP_SHIFT 20
#define DRA7XX_EVE3_STATDEP_SHIFT 21
#define DRA7XX_EVE4_STATDEP_SHIFT 22
#define DRA7XX_GMAC_STATDEP_SHIFT 25
#define DRA7XX_GPU_STATDEP_SHIFT 10
#define DRA7XX_IPU1_STATDEP_SHIFT 23
#define DRA7XX_IPU2_STATDEP_SHIFT 0
#define DRA7XX_IPU_STATDEP_SHIFT 24
#define DRA7XX_IVA_STATDEP_SHIFT 2
#define DRA7XX_L3INIT_STATDEP_SHIFT 7
#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
#define DRA7XX_L4CFG_STATDEP_SHIFT 12
#define DRA7XX_L4PER2_STATDEP_SHIFT 26
#define DRA7XX_L4PER3_STATDEP_SHIFT 27
#define DRA7XX_L4PER_STATDEP_SHIFT 13
#define DRA7XX_L4SEC_STATDEP_SHIFT 14
#define DRA7XX_PCIE_STATDEP_SHIFT 29
#define DRA7XX_VPE_STATDEP_SHIFT 28
#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
#endif

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/*
* DRA7xx CM1 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
#include "cm_44xx_54xx.h"
/* CM1 base address */
#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
/* CM_CORE_AON instances */
#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
/* CM_CORE_AON clockdomain register offsets (from instance start) */
#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
/* CM_CORE_AON */
/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
#endif

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arch/arm/mach-omap2/cm2_7xx.h Normal file
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/*
* DRA7xx CM2 instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
#include "cm_44xx_54xx.h"
/* CM2 base address */
#define DRA7XX_CM_CORE_BASE 0x4a008000
#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
/* CM_CORE instances */
#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
#define DRA7XX_CM_CORE_COREAON_INST 0x0600
#define DRA7XX_CM_CORE_CORE_INST 0x0700
#define DRA7XX_CM_CORE_IVA_INST 0x0f00
#define DRA7XX_CM_CORE_CAM_INST 0x1000
#define DRA7XX_CM_CORE_DSS_INST 0x1100
#define DRA7XX_CM_CORE_GPU_INST 0x1200
#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
#define DRA7XX_CM_CORE_L4PER_INST 0x1700
#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
/* CM_CORE clockdomain register offsets (from instance start) */
#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
/* CM_CORE */
/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
/* CM_CORE.CKGEN_CM_CORE register offsets */
#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
/* CM_CORE.COREAON_CM_CORE register offsets */
#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
/* CM_CORE.CORE_CM_CORE register offsets */
#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
/* CM_CORE.IVA_CM_CORE register offsets */
#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
/* CM_CORE.CAM_CM_CORE register offsets */
#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
/* CM_CORE.DSS_CM_CORE register offsets */
#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
/* CM_CORE.GPU_CM_CORE register offsets */
#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
/* CM_CORE.L3INIT_CM_CORE register offsets */
#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
/* CM_CORE.L4PER_CM_CORE register offsets */
#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
#endif

5
arch/arm/mach-omap2/io.c
View File

@ -665,6 +665,11 @@ void __init dra7xx_init_early(void)
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
omap_prm_base_init();
omap_cm_base_init();
omap44xx_prm_init();
dra7xx_powerdomains_init();
dra7xx_clockdomains_init();
dra7xx_hwmod_init();
omap_hwmod_init_postsetup();
}
#endif

1
arch/arm/mach-omap2/omap_hwmod.h
View File

@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int dra7xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);

2724
arch/arm/mach-omap2/omap_hwmod_7xx_data.c Normal file
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File diff suppressed because it is too large Load Diff

1
arch/arm/mach-omap2/powerdomain.h
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@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
extern void dra7xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;

454
arch/arm/mach-omap2/powerdomains7xx_data.c Normal file
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@ -0,0 +1,454 @@
/*
* DRA7xx Power domains framework
*
* Copyright (C) 2009-2013 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Generated by code originally written by:
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
* Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include "powerdomain.h"
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"
/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
.name = "iva_pwrdm",
.prcm_offs = DRA7XX_PRM_IVA_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* rtc_7xx_pwrdm: */
static struct powerdomain rtc_7xx_pwrdm = {
.name = "rtc_pwrdm",
.prcm_offs = DRA7XX_PRM_RTC_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_7xx_pwrdm = {
.name = "custefuse_pwrdm",
.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
.name = "ipu_pwrdm",
.prcm_offs = DRA7XX_PRM_IPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* aessmem */
[1] = PWRSTS_OFF_RET, /* periphmem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dss_7xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_7xx_pwrdm = {
.name = "dss_pwrdm",
.prcm_offs = DRA7XX_PRM_DSS_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dss_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l4per_7xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_7xx_pwrdm = {
.name = "l4per_pwrdm",
.prcm_offs = DRA7XX_PRM_L4PER_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
[1] = PWRSTS_OFF_RET, /* retained_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* nonretained_bank */
[1] = PWRSTS_OFF_RET, /* retained_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gpu_7xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_7xx_pwrdm = {
.name = "gpu_pwrdm",
.prcm_offs = DRA7XX_PRM_GPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gpu_mem */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkupaon_7xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_7xx_pwrdm = {
.name = "wkupaon_pwrdm",
.prcm_offs = DRA7XX_PRM_WKUPAON_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
.banks = 1,
.pwrsts_mem_ret = {
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* wkup_bank */
},
};
/* core_7xx_pwrdm: CORE power domain */
static struct powerdomain core_7xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = DRA7XX_PRM_CORE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRSTS_OFF_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ipu_l2ram */
[4] = PWRSTS_OFF_RET, /* ipu_unicache */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_7xx_pwrdm = {
.name = "coreaon_pwrdm",
.prcm_offs = DRA7XX_PRM_COREAON_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_ON,
};
/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_7xx_pwrdm = {
.name = "cpu0_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu0_l1 */
},
};
/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_7xx_pwrdm = {
.name = "cpu1_pwrdm",
.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cpu1_l1 */
},
};
/* vpe_7xx_pwrdm: */
static struct powerdomain vpe_7xx_pwrdm = {
.name = "vpe_pwrdm",
.prcm_offs = DRA7XX_PRM_VPE_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* vpe_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* vpe_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_7xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = DRA7XX_PRM_MPU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_RET, /* mpu_ram */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* mpu_l2 */
[1] = PWRSTS_OFF_RET, /* mpu_ram */
},
};
/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
static struct powerdomain l3init_7xx_pwrdm = {
.name = "l3init_pwrdm",
.prcm_offs = DRA7XX_PRM_L3INIT_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* gmac_bank */
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* gmac_bank */
[1] = PWRSTS_OFF_RET, /* l3init_bank1 */
[2] = PWRSTS_OFF_RET, /* l3init_bank2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve3_7xx_pwrdm: */
static struct powerdomain eve3_7xx_pwrdm = {
.name = "eve3_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE3_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve3_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve3_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* emu_7xx_pwrdm: Emulation power domain */
static struct powerdomain emu_7xx_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = DRA7XX_PRM_EMU_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* emu_bank */
},
};
/* dsp2_7xx_pwrdm: */
static struct powerdomain dsp2_7xx_pwrdm = {
.name = "dsp2_pwrdm",
.prcm_offs = DRA7XX_PRM_DSP2_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp2_edma */
[1] = PWRSTS_OFF_RET, /* dsp2_l1 */
[2] = PWRSTS_OFF_RET, /* dsp2_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dsp1_7xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp1_7xx_pwrdm = {
.name = "dsp1_pwrdm",
.prcm_offs = DRA7XX_PRM_DSP1_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 3,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* dsp1_edma */
[1] = PWRSTS_OFF_RET, /* dsp1_l1 */
[2] = PWRSTS_OFF_RET, /* dsp1_l2 */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_7xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_7xx_pwrdm = {
.name = "cam_pwrdm",
.prcm_offs = DRA7XX_PRM_CAM_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* vip_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* vip_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve4_7xx_pwrdm: */
static struct powerdomain eve4_7xx_pwrdm = {
.name = "eve4_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE4_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve4_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve4_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve2_7xx_pwrdm: */
static struct powerdomain eve2_7xx_pwrdm = {
.name = "eve2_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE2_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve2_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve2_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* eve1_7xx_pwrdm: */
static struct powerdomain eve1_7xx_pwrdm = {
.name = "eve1_pwrdm",
.prcm_offs = DRA7XX_PRM_EVE1_INST,
.prcm_partition = DRA7XX_PRM_PARTITION,
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* eve1_bank */
},
.pwrsts_mem_on = {
[0] = PWRSTS_OFF_RET, /* eve1_bank */
},
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
* The following power domains are not under SW control
*
* mpuaon
* mmaon
*/
/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
&iva_7xx_pwrdm,
&rtc_7xx_pwrdm,
&custefuse_7xx_pwrdm,
&ipu_7xx_pwrdm,
&dss_7xx_pwrdm,
&l4per_7xx_pwrdm,
&gpu_7xx_pwrdm,
&wkupaon_7xx_pwrdm,
&core_7xx_pwrdm,
&coreaon_7xx_pwrdm,
&cpu0_7xx_pwrdm,
&cpu1_7xx_pwrdm,
&vpe_7xx_pwrdm,
&mpu_7xx_pwrdm,
&l3init_7xx_pwrdm,
&eve3_7xx_pwrdm,
&emu_7xx_pwrdm,
&dsp2_7xx_pwrdm,
&dsp1_7xx_pwrdm,
&cam_7xx_pwrdm,
&eve4_7xx_pwrdm,
&eve2_7xx_pwrdm,
&eve1_7xx_pwrdm,
NULL
};
void __init dra7xx_powerdomains_init(void)
{
pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
pwrdm_register_pwrdms(powerdomains_dra7xx);
pwrdm_complete_init();
}

5
arch/arm/mach-omap2/prcm44xx.h
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@ -38,6 +38,11 @@
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
#define DRA7XX_PRM_PARTITION 1
#define DRA7XX_CM_CORE_AON_PARTITION 2
#define DRA7XX_CM_CORE_PARTITION 3
#define DRA7XX_MPU_PRCM_PARTITION 5
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one

78
arch/arm/mach-omap2/prcm_mpu7xx.h Normal file
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@ -0,0 +1,78 @@
/*
* DRA7xx PRCM MPU instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
#include "prcm_mpu_44xx_54xx.h"
#define DRA7XX_PRCM_MPU_BASE 0x48243000
#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
/* MPU_PRCM instances */
#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
/* PRCM_MPU clockdomain register offsets (from instance start) */
#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
/* MPU_PRCM */
/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
#endif

12
arch/arm/mach-omap2/prm44xx.c
View File

@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
return 0;
}
static int omap4_check_vcvp(void)
{
/* No VC/VP on dra7xx devices */
if (soc_is_dra7xx())
return 0;
return 1;
}
struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
.pwrdm_wait_transition = omap4_pwrdm_wait_transition,
.pwrdm_has_voltdm = omap4_check_vcvp,
};
/*
@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
int __init omap44xx_prm_init(void)
{
if (!cpu_is_omap44xx() && !soc_is_omap54xx())
if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
return 0;
return prm_register(&omap44xx_prm_ll_data);

678
arch/arm/mach-omap2/prm7xx.h Normal file
View File

@ -0,0 +1,678 @@
/*
* DRA7xx PRM instance offset macros
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
*
* Generated by code originally written by:
* Paul Walmsley (paul@pwsan.com)
* Rajendra Nayak (rnayak@ti.com)
* Benoit Cousson (b-cousson@ti.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
* with the public linux-omap@vger.kernel.org mailing list and the
* authors above to ensure that the autogeneration scripts are kept
* up-to-date with the file contents.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
#include "prm44xx_54xx.h"
#include "prcm-common.h"
#include "prm.h"
#define DRA7XX_PRM_BASE 0x4ae06000
#define DRA7XX_PRM_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
/* PRM instances */
#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
#define DRA7XX_PRM_CKGEN_INST 0x0100
#define DRA7XX_PRM_MPU_INST 0x0300
#define DRA7XX_PRM_DSP1_INST 0x0400
#define DRA7XX_PRM_IPU_INST 0x0500
#define DRA7XX_PRM_COREAON_INST 0x0628
#define DRA7XX_PRM_CORE_INST 0x0700
#define DRA7XX_PRM_IVA_INST 0x0f00
#define DRA7XX_PRM_CAM_INST 0x1000
#define DRA7XX_PRM_DSS_INST 0x1100
#define DRA7XX_PRM_GPU_INST 0x1200
#define DRA7XX_PRM_L3INIT_INST 0x1300
#define DRA7XX_PRM_L4PER_INST 0x1400
#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
#define DRA7XX_PRM_WKUPAON_INST 0x1724
#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
#define DRA7XX_PRM_EMU_INST 0x1900
#define DRA7XX_PRM_EMU_CM_INST 0x1a00
#define DRA7XX_PRM_DSP2_INST 0x1b00
#define DRA7XX_PRM_EVE1_INST 0x1b40
#define DRA7XX_PRM_EVE2_INST 0x1b80
#define DRA7XX_PRM_EVE3_INST 0x1bc0
#define DRA7XX_PRM_EVE4_INST 0x1c00
#define DRA7XX_PRM_RTC_INST 0x1c60
#define DRA7XX_PRM_VPE_INST 0x1c80
#define DRA7XX_PRM_DEVICE_INST 0x1d00
#define DRA7XX_PRM_INSTR_INST 0x1f00
/* PRM clockdomain register offsets (from instance start) */
#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
/* PRM */
/* PRM.OCP_SOCKET_PRM register offsets */
#define DRA7XX_REVISION_PRM_OFFSET 0x0000
#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
/* PRM.CKGEN_PRM register offsets */
#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
/* PRM.MPU_PRM register offsets */
#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
/* PRM.DSP1_PRM register offsets */
#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
/* PRM.IPU_PRM register offsets */
#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
/* PRM.COREAON_PRM register offsets */
#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
/* PRM.CORE_PRM register offsets */
#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
/* PRM.IVA_PRM register offsets */
#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
/* PRM.CAM_PRM register offsets */
#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
/* PRM.DSS_PRM register offsets */
#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
/* PRM.GPU_PRM register offsets */
#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
/* PRM.L3INIT_PRM register offsets */
#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
/* PRM.L4PER_PRM register offsets */
#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
/* PRM.CUSTEFUSE_PRM register offsets */
#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
/* PRM.WKUPAON_PRM register offsets */
#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
/* PRM.WKUPAON_CM register offsets */
#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
/* PRM.EMU_PRM register offsets */
#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
/* PRM.EMU_CM register offsets */
#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
/* PRM.DSP2_PRM register offsets */
#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
/* PRM.EVE1_PRM register offsets */
#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
/* PRM.EVE2_PRM register offsets */
#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
/* PRM.EVE3_PRM register offsets */
#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
/* PRM.EVE4_PRM register offsets */
#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
/* PRM.RTC_PRM register offsets */
#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
/* PRM.VPE_PRM register offsets */
#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
/* PRM.DEVICE_PRM register offsets */
#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
#define DRA7XX_PRM_RSTST_OFFSET 0x0004
#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
#endif

18
arch/arm/mach-omap2/prminst44xx.c
View File

@ -20,10 +20,13 @@
#include "common.h"
#include "prcm-common.h"
#include "prm44xx.h"
#include "prm54xx.h"
#include "prm7xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prcm_mpu44xx.h"
#include "soc.h"
static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
void omap4_prminst_global_warm_sw_reset(void)
{
u32 v;
s16 dev_inst;
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
OMAP4430_PRM_DEVICE_INST,
OMAP4_PRM_RSTCTRL_OFFSET);
if (cpu_is_omap44xx())
dev_inst = OMAP4430_PRM_DEVICE_INST;
else if (soc_is_omap54xx())
dev_inst = OMAP54XX_PRM_DEVICE_INST;
else if (soc_is_dra7xx())
dev_inst = DRA7XX_PRM_DEVICE_INST;
else
return;
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
OMAP4_PRM_RSTCTRL_OFFSET);
v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
OMAP4430_PRM_DEVICE_INST,