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Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

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Cross-merge networking fixes after downstream PR.

Conflicts:

include/linux/filter.h
kernel/bpf/core.c
  66e13b615a ("bpf: verifier: prevent userspace memory access")
  d503a04f8b ("bpf: Add support for certain atomics in bpf_arena to x86 JIT")
https://lore.kernel.org/all/20240429114939.210328b0@canb.auug.org.au/

No adjacent changes.

Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2024-05-02 12:05:13 -07:00
commit e958da0ddb
306 changed files with 2458 additions and 1536 deletions
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1
.mailmap
View File

@ -512,6 +512,7 @@ Praveen BP <praveenbp@ti.com>
Pradeep Kumar Chitrapu <quic_pradeepc@quicinc.com> <pradeepc@codeaurora.org>
Prasad Sodagudi <quic_psodagud@quicinc.com> <psodagud@codeaurora.org>
Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
Puranjay Mohan <puranjay@kernel.org> <puranjay12@gmail.com>
Qais Yousef <qyousef@layalina.io> <qais.yousef@imgtec.com>
Qais Yousef <qyousef@layalina.io> <qais.yousef@arm.com>
Quentin Monnet <qmo@kernel.org> <quentin.monnet@netronome.com>

3
Documentation/admin-guide/kernel-parameters.txt
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@ -3423,6 +3423,9 @@
arch-independent options, each of which is an
aggregation of existing arch-specific options.
Note, "mitigations" is supported if and only if the
kernel was built with CPU_MITIGATIONS=y.
off
Disable all optional CPU mitigations. This
improves system performance, but it may also

6
Documentation/core-api/workqueue.rst
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@ -671,7 +671,7 @@ configuration, worker pools and how workqueues map to the pools: ::
events_unbound unbound 9 9 10 10 8
events_freezable percpu 0 2 4 6
events_power_efficient percpu 0 2 4 6
events_freezable_power_ percpu 0 2 4 6
events_freezable_pwr_ef percpu 0 2 4 6
rcu_gp percpu 0 2 4 6
rcu_par_gp percpu 0 2 4 6
slub_flushwq percpu 0 2 4 6
@ -694,7 +694,7 @@ Use tools/workqueue/wq_monitor.py to monitor workqueue operations: ::
events_unbound 38306 0 0.1 - 7 - -
events_freezable 0 0 0.0 0 0 - -
events_power_efficient 29598 0 0.2 0 0 - -
events_freezable_power_ 10 0 0.0 0 0 - -
events_freezable_pwr_ef 10 0 0.0 0 0 - -
sock_diag_events 0 0 0.0 0 0 - -
total infl CPUtime CPUhog CMW/RPR mayday rescued
@ -704,7 +704,7 @@ Use tools/workqueue/wq_monitor.py to monitor workqueue operations: ::
events_unbound 38322 0 0.1 - 7 - -
events_freezable 0 0 0.0 0 0 - -
events_power_efficient 29603 0 0.2 0 0 - -
events_freezable_power_ 10 0 0.0 0 0 - -
events_freezable_pwr_ef 10 0 0.0 0 0 - -
sock_diag_events 0 0 0.0 0 0 - -
...

5
Documentation/devicetree/bindings/eeprom/at24.yaml
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@ -68,14 +68,10 @@ properties:
pattern: cs16$
- items:
pattern: c32$
- items:
pattern: c32d-wl$
- items:
pattern: cs32$
- items:
pattern: c64$
- items:
pattern: c64d-wl$
- items:
pattern: cs64$
- items:
@ -136,6 +132,7 @@ properties:
- renesas,r1ex24128
- samsung,s524ad0xd1
- const: atmel,24c128
- pattern: '^atmel,24c(32|64)d-wl$' # Actual vendor is st
label:
description: Descriptive name of the EEPROM.

2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
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@ -120,7 +120,9 @@ additionalProperties:
slew-rate: true
gpio-hog: true
gpios: true
input: true
input-enable: true
output-enable: true
output-high: true
output-low: true
line-name: true

1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
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@ -171,6 +171,7 @@ allOf:
unevaluatedProperties: false
pcie-phy:
type: object
description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt

2
Documentation/rust/arch-support.rst
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@ -16,7 +16,7 @@ support corresponds to ``S`` values in the ``MAINTAINERS`` file.
Architecture Level of support Constraints
============= ================ ==============================================
``arm64`` Maintained Little Endian only.
``loongarch`` Maintained -
``loongarch`` Maintained \-
``um`` Maintained ``x86_64`` only.
``x86`` Maintained ``x86_64`` only.
============= ================ ==============================================

7
Documentation/timers/no_hz.rst
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@ -129,11 +129,8 @@ adaptive-tick CPUs: At least one non-adaptive-tick CPU must remain
online to handle timekeeping tasks in order to ensure that system
calls like gettimeofday() returns accurate values on adaptive-tick CPUs.
(This is not an issue for CONFIG_NO_HZ_IDLE=y because there are no running
user processes to observe slight drifts in clock rate.) Therefore, the
boot CPU is prohibited from entering adaptive-ticks mode. Specifying a
"nohz_full=" mask that includes the boot CPU will result in a boot-time
error message, and the boot CPU will be removed from the mask. Note that
this means that your system must have at least two CPUs in order for
user processes to observe slight drifts in clock rate.) Note that this
means that your system must have at least two CPUs in order for
CONFIG_NO_HZ_FULL=y to do anything for you.
Finally, adaptive-ticks CPUs must have their RCU callbacks offloaded.

398
Documentation/translations/zh_CN/core-api/workqueue.rst
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@ -7,12 +7,13 @@
司延腾 Yanteng Si <siyanteng@loongson.cn>
周彬彬 Binbin Zhou <zhoubinbin@loongson.cn>
陈兴友 Xingyou Chen <rockrush@rockwork.org>
.. _cn_workqueue.rst:
=========================
并发管理的工作队列 (cmwq)
=========================
========
工作队列
========
:日期: September, 2010
:作者: Tejun Heo <tj@kernel.org>
@ -22,7 +23,7 @@
简介
====
在很多情况下，需要一个异步进程的执行环境，工作队列（wq）API是这种情况下
在很多情况下，需要一个异步的程序执行环境，工作队列（wq）API是这种情况下
最常用的机制。
当需要这样一个异步执行上下文时，一个描述将要执行的函数的工作项（work，
@ -34,8 +35,8 @@
队列时，工作者又开始执行。
为什么要cmwq?
=============
为什么要有并发管理工作队列?
===========================
在最初的wq实现中，多线程（MT）wq在每个CPU上有一个工作者线程，而单线程
（ST）wq在全系统有一个工作者线程。一个MT wq需要保持与CPU数量相同的工
@ -73,9 +74,11 @@
向该函数的工作项，并在工作队列中排队等待该工作项。（就是挂到workqueue
队列里面去）
特定目的线程，称为工作线程（工作者），一个接一个地执行队列中的功能。
如果没有工作项排队，工作者线程就会闲置。这些工作者线程被管理在所谓
的工作者池中。
工作项可以在线程或BH(软中断)上下文中执行。
对于由线程执行的工作队列，被称为（内核）工作者（[k]worker）的特殊
线程会依次执行其中的函数。如果没有工作项排队，工作者线程就会闲置。
这些工作者线程被管理在所谓的工作者池中。
cmwq设计区分了面向用户的工作队列，子系统和驱动程序在上面排队工作，
以及管理工作者池和处理排队工作项的后端机制。
@ -84,6 +87,10 @@ cmwq设计区分了面向用户的工作队列，子系统和驱动程序在上
优先级的工作项，还有一些额外的工作者池，用于服务未绑定工作队列的工
作项目——这些后备池的数量是动态的。
BH工作队列使用相同的结构。然而，由于同一时间只可能有一个执行上下文，
不需要担心并发问题。每个CPU上的BH工作者池只包含一个用于表示BH执行
上下文的虚拟工作者。BH工作队列可以被看作软中断的便捷接口。
当他们认为合适的时候，子系统和驱动程序可以通过特殊的
``workqueue API`` 函数创建和排队工作项。他们可以通过在工作队列上
设置标志来影响工作项执行方式的某些方面，他们把工作项放在那里。这些
@ -95,9 +102,9 @@ cmwq设计区分了面向用户的工作队列，子系统和驱动程序在上
否则一个绑定的工作队列的工作项将被排在与发起线程运行的CPU相关的普
通或高级工作工作者池的工作项列表中。
对于任何工作者池的实施，管理并发水平（有多少执行上下文处于活动状
态）是一个重要问题。最低水平是为了节省资源，而饱和水平是指系统被
充分使用。
对于任何线程池的实施，管理并发水平（有多少执行上下文处于活动状
态）是一个重要问题。cmwq试图将并发保持在一个尽可能低且充足的
水平。最低水平是为了节省资源，而充足是为了使系统能被充分使用。
每个与实际CPU绑定的worker-pool通过钩住调度器来实现并发管理。每当
一个活动的工作者被唤醒或睡眠时，工作者池就会得到通知，并跟踪当前可
@ -140,6 +147,17 @@ workqueue将自动创建与属性相匹配的后备工作者池。调节并发
``flags``
---------
``WQ_BH``
BH工作队列可以被看作软中断的便捷接口。它总是每个CPU一份，
其中的各个工作项也会按在队列中的顺序，被所属CPU在软中断
上下文中执行。
BH工作队列的 ``max_active`` 值必须为0，且只能单独或和
``WQ_HIGHPRI`` 标志组合使用。
BH工作项不可以睡眠。像延迟排队、冲洗、取消等所有其他特性
都是支持的。
``WQ_UNBOUND``
排队到非绑定wq的工作项由特殊的工作者池提供服务，这些工作者不
绑定在任何特定的CPU上。这使得wq表现得像一个简单的执行环境提
@ -184,25 +202,21 @@ workqueue将自动创建与属性相匹配的后备工作者池。调节并发
--------------
``@max_active`` 决定了每个CPU可以分配给wq的工作项的最大执行上
下文数量。例如，如果 ``@max_active为16`` ，每个CPU最多可以同
时执行16个wq的工作项。
下文数量。例如，如果 ``@max_active`` 为16 ，每个CPU最多可以同
时执行16个wq的工作项。它总是每CPU属性，即便对于未绑定 wq。
目前，对于一个绑定的wq， ``@max_active`` 的最大限制是512，当指
定为0时使用的默认值是256。对于非绑定的wq，其限制是512和
4 * ``num_possible_cpus()`` 中的较高值。这些值被选得足够高，所
以它们不是限制性因素，同时会在失控情况下提供保护。
``@max_active`` 的最大限制是512，当指定为0时使用的默认值是256。
这些值被选得足够高，所以它们不是限制性因素，同时会在失控情况下提供
保护。
一个wq的活动工作项的数量通常由wq的用户来调节，更具体地说，是由用
户在同一时间可以排列多少个工作项来调节。除非有特定的需求来控制活动
工作项的数量，否则建议指定 为"0"。
一些用户依赖于ST wq的严格执行顺序。 ``@max_active`` 为1和 ``WQ_UNBOUND``
的组合用来实现这种行为。这种wq上的工作项目总是被排到未绑定的工作池
中，并且在任何时候都只有一个工作项目处于活动状态，从而实现与ST wq相
同的排序属性。
在目前的实现中，上述配置只保证了特定NUMA节点内的ST行为。相反，
``alloc_ordered_workqueue()`` 应该被用来实现全系统的ST行为。
一些用户依赖于任意时刻最多只有一个工作项被执行，且各工作项被按队列中
顺序处理带来的严格执行顺序。``@max_active`` 为1和 ``WQ_UNBOUND``
的组合曾被用来实现这种行为，现在不用了。请使用
``alloc_ordered_workqueue()`` 。
执行场景示例
@ -285,7 +299,7 @@ And with cmwq with ``@max_active`` >= 3, ::
* 除非有特殊需要，建议使用0作为@max_active。在大多数使用情
况下，并发水平通常保持在默认限制之下。
* 一个wq作为前进进度保证（WQ_MEM_RECLAIM，冲洗（flush）和工
* 一个wq作为前进进度保证，``WQ_MEM_RECLAIM`` ，冲洗（flush）和工
作项属性的域。不涉及内存回收的工作项，不需要作为工作项组的一
部分被刷新，也不需要任何特殊属性，可以使用系统中的一个wq。使
用专用wq和系统wq在执行特性上没有区别。
@ -294,6 +308,337 @@ And with cmwq with ``@max_active`` >= 3, ::
益的，因为wq操作和工作项执行中的定位水平提高了。
亲和性作用域
============
一个非绑定工作队列根据其亲和性作用域来对CPU进行分组以提高缓存
局部性。比如如果一个工作队列使用默认的“cache”亲和性作用域，
它将根据最后一级缓存的边界来分组处理器。这个工作队列上的工作项
将被分配给一个与发起CPU共用最后级缓存的处理器上的工作者。根据
``affinity_strict`` 的设置，工作者在启动后可能被允许移出
所在作用域，也可能不被允许。
工作队列目前支持以下亲和性作用域。
``default``
使用模块参数 ``workqueue.default_affinity_scope`` 指定
的作用域，该参数总是会被设为以下作用域中的一个。
``cpu``
CPU不被分组。一个CPU上发起的工作项会被同一CPU上的工作者执行。
这使非绑定工作队列表现得像是不含并发管理的每CPU工作队列。
``smt``
CPU被按SMT边界分组。这通常意味着每个物理CPU核上的各逻辑CPU会
被分进同一组。
``cache``
CPU被按缓存边界分组。采用哪个缓存边界由架构代码决定。很多情况
下会使用L3。这是默认的亲和性作用域。
``numa``
CPU被按NUMA边界分组。
``system``
所有CPU被放在同一组。工作队列不尝试在临近发起CPU的CPU上运行
工作项。
默认的亲和性作用域可以被模块参数 ``workqueue.default_affinity_scope``
修改，特定工作队列的亲和性作用域可以通过 ``apply_workqueue_attrs()``
被更改。
如果设置了 ``WQ_SYSFS`` ，工作队列会在它的 ``/sys/devices/virtual/workqueue/WQ_NAME/``
目录中有以下亲和性作用域相关的接口文件。
``affinity_scope``
读操作以查看当前的亲和性作用域。写操作用于更改设置。
当前作用域是默认值时，当前生效的作用域也可以被从这个文件中
读到（小括号内），例如 ``default (cache)`` 。
``affinity_strict``
默认值0表明亲和性作用域不是严格的。当一个工作项开始执行时，
工作队列尽量尝试使工作者处于亲和性作用域内，称为遣返。启动后，
调度器可以自由地将工作者调度到系统中任意它认为合适的地方去。
这使得在保留使用其他CPU（如果必需且有可用）能力的同时，
还能从作用域局部性上获益。
如果设置为1，作用域内的所有工作者将被保证总是处于作用域内。
这在跨亲和性作用域会导致如功耗、负载隔离等方面的潜在影响时
会有用。严格的NUMA作用域也可用于和旧版内核中工作队列的行为
保持一致。
亲和性作用域与性能
==================
如果非绑定工作队列的行为对绝大多数使用场景来说都是最优的，
不需要更多调节，就完美了。很不幸，在当前内核中，重度使用
工作队列时，需要在局部性和利用率间显式地作一个明显的权衡。
更高的局部性带来更高效率，也就是相同数量的CPU周期内可以做
更多工作。然而，如果发起者没能将工作项充分地分散在亲和性
作用域间，更高的局部性也可能带来更低的整体系统利用率。以下
dm-crypt 的性能测试清楚地阐明了这一取舍。
测试运行在一个12核24线程、4个L3缓存的处理器（AMD Ryzen
9 3900x）上。为保持一致性，关闭CPU超频。 ``/dev/dm-0``
是NVME SSD（三星 990 PRO）上创建，用 ``cryptsetup``
以默认配置打开的一个 dm-crypt 设备。
场景 1: 机器上遍布着有充足的发起者和工作量
------------------------------------------
使用命令：::
$ fio --filename=/dev/dm-0 --direct=1 --rw=randrw --bs=32k --ioengine=libaio \
--iodepth=64 --runtime=60 --numjobs=24 --time_based --group_reporting \
--name=iops-test-job --verify=sha512
这里有24个发起者，每个同时发起64个IO。 ``--verify=sha512``
使得 ``fio`` 每次生成和读回内容受发起者和 ``kcryptd``
间的执行局部性影响。下面是基于不同 ``kcryptd`` 的亲和性
作用域设置，各经过五次测试得到的读取带宽和CPU利用率数据。
.. list-table::
:widths: 16 20 20
:header-rows: 1
* - 亲和性
- 带宽 (MiBps)
- CPU利用率（%）
* - system
- 1159.40 ±1.34
- 99.31 ±0.02
* - cache
- 1166.40 ±0.89
- 99.34 ±0.01
* - cache (strict)
- 1166.00 ±0.71
- 99.35 ±0.01
在系统中分布着足够多发起者的情况下，不论严格与否，“cache”
没有表现得更差。三种配置均使整个机器达到饱和，但由于提高了
局部性，缓存相关的两种有0.6%的（带宽）提升。
场景 2: 更少发起者，足以达到饱和的工作量
----------------------------------------
使用命令：::
$ fio --filename=/dev/dm-0 --direct=1 --rw=randrw --bs=32k \
--ioengine=libaio --iodepth=64 --runtime=60 --numjobs=8 \
--time_based --group_reporting --name=iops-test-job --verify=sha512
与上一个场景唯一的区别是 ``--numjobs=8``。 发起者数量
减少为三分之一，但仍然有足以使系统达到饱和的工作总量。
.. list-table::
:widths: 16 20 20
:header-rows: 1
* - 亲和性
- 带宽 (MiBps)
- CPU利用率（%）
* - system
- 1155.40 ±0.89
- 97.41 ±0.05
* - cache
- 1154.40 ±1.14
- 96.15 ±0.09
* - cache (strict)
- 1112.00 ±4.64
- 93.26 ±0.35
这里有超过使系统达到饱和所需的工作量。“system”和“cache”
都接近但并未使机器完全饱和。“cache”消耗更少的CPU但更高的
效率使其得到和“system”相同的带宽。
八个发起者盘桓在四个L3缓存作用域间仍然允许“cache (strict)”
几乎使机器饱和，但缺少对工作的保持（不移到空闲处理器上）
开始带来3.7%的带宽损失。
场景 3: 更少发起者，不充足的工作量
----------------------------------
使用命令：::
$ fio --filename=/dev/dm-0 --direct=1 --rw=randrw --bs=32k \
--ioengine=libaio --iodepth=64 --runtime=60 --numjobs=4 \
--time_based --group_reporting --name=iops-test-job --verify=sha512
再次，唯一的区别是 ``--numjobs=4``。由于发起者减少到四个，
现在没有足以使系统饱和的工作量，带宽变得依赖于完成时延。
.. list-table::
:widths: 16 20 20
:header-rows: 1
* - 亲和性
- 带宽 (MiBps)
- CPU利用率（%）
* - system
- 993.60 ±1.82
- 75.49 ±0.06
* - cache
- 973.40 ±1.52
- 74.90 ±0.07
* - cache (strict)
- 828.20 ±4.49
- 66.84 ±0.29
现在，局部性和利用率间的权衡更清晰了。“cache”展示出相比
“system”2%的带宽损失，而“cache (strict)”跌到20%。
结论和建议
----------
在以上试验中，虽然一致并且也明显，但“cache”亲和性作用域
相比“system”的性能优势并不大。然而，这影响是依赖于作用域
间距离的，在更复杂的处理器拓扑下可能有更明显的影响。
虽然这些情形下缺少工作保持是有坏处的，但比“cache (strict)”
好多了，而且最大化工作队列利用率的需求也并不常见。因此，
“cache”是非绑定池的默认亲和性作用域。
* 由于不存在一个适用于大多数场景的选择，对于可能需要消耗
大量CPU的工作队列，建议通过 ``apply_workqueue_attrs()``
进行（专门）配置，并考虑是否启用 ``WQ_SYSFS``。
* 设置了严格“cpu”亲和性作用域的非绑定工作队列，它的行为与
``WQ_CPU_INTENSIVE`` 每CPU工作队列一样。后者没有真正
优势，而前者提供了大幅度的灵活性。
* 亲和性作用域是从Linux v6.5起引入的。为了模拟旧版行为，
可以使用严格的“numa”亲和性作用域。
* 不严格的亲和性作用域中，缺少工作保持大概缘于调度器。内核
为什么没能维护好大多数场景下的工作保持，把事情作对，还没有
理论上的解释。因此，未来调度器的改进可能会使我们不再需要
这些调节项。
检查配置
========
使用 tools/workqueue/wq_dump.py（drgn脚本） 来检查未
绑定CPU的亲和性配置，工作者池，以及工作队列如何映射到池上: ::
$ tools/workqueue/wq_dump.py
Affinity Scopes
===============
wq_unbound_cpumask=0000000f
CPU
nr_pods 4
pod_cpus [0]=00000001 [1]=00000002 [2]=00000004 [3]=00000008
pod_node [0]=0 [1]=0 [2]=1 [3]=1
cpu_pod [0]=0 [1]=1 [2]=2 [3]=3
SMT
nr_pods 4
pod_cpus [0]=00000001 [1]=00000002 [2]=00000004 [3]=00000008
pod_node [0]=0 [1]=0 [2]=1 [3]=1
cpu_pod [0]=0 [1]=1 [2]=2 [3]=3
CACHE (default)
nr_pods 2
pod_cpus [0]=00000003 [1]=0000000c
pod_node [0]=0 [1]=1
cpu_pod [0]=0 [1]=0 [2]=1 [3]=1
NUMA
nr_pods 2
pod_cpus [0]=00000003 [1]=0000000c
pod_node [0]=0 [1]=1
cpu_pod [0]=0 [1]=0 [2]=1 [3]=1
SYSTEM
nr_pods 1
pod_cpus [0]=0000000f
pod_node [0]=-1
cpu_pod [0]=0 [1]=0 [2]=0 [3]=0
Worker Pools
============
pool[00] ref= 1 nice= 0 idle/workers= 4/ 4 cpu= 0
pool[01] ref= 1 nice=-20 idle/workers= 2/ 2 cpu= 0
pool[02] ref= 1 nice= 0 idle/workers= 4/ 4 cpu= 1
pool[03] ref= 1 nice=-20 idle/workers= 2/ 2 cpu= 1
pool[04] ref= 1 nice= 0 idle/workers= 4/ 4 cpu= 2
pool[05] ref= 1 nice=-20 idle/workers= 2/ 2 cpu= 2
pool[06] ref= 1 nice= 0 idle/workers= 3/ 3 cpu= 3
pool[07] ref= 1 nice=-20 idle/workers= 2/ 2 cpu= 3
pool[08] ref=42 nice= 0 idle/workers= 6/ 6 cpus=0000000f
pool[09] ref=28 nice= 0 idle/workers= 3/ 3 cpus=00000003
pool[10] ref=28 nice= 0 idle/workers= 17/ 17 cpus=0000000c
pool[11] ref= 1 nice=-20 idle/workers= 1/ 1 cpus=0000000f
pool[12] ref= 2 nice=-20 idle/workers= 1/ 1 cpus=00000003
pool[13] ref= 2 nice=-20 idle/workers= 1/ 1 cpus=0000000c
Workqueue CPU -> pool
=====================
[ workqueue \ CPU 0 1 2 3 dfl]
events percpu 0 2 4 6
events_highpri percpu 1 3 5 7
events_long percpu 0 2 4 6
events_unbound unbound 9 9 10 10 8
events_freezable percpu 0 2 4 6
events_power_efficient percpu 0 2 4 6
events_freezable_power_ percpu 0 2 4 6
rcu_gp percpu 0 2 4 6
rcu_par_gp percpu 0 2 4 6
slub_flushwq percpu 0 2 4 6
netns ordered 8 8 8 8 8
...
参见命令的帮助消息以获取更多信息。
监视
====
使用 tools/workqueue/wq_monitor.py 来监视工作队列的运行： ::
$ tools/workqueue/wq_monitor.py events
total infl CPUtime CPUhog CMW/RPR mayday rescued
events 18545 0 6.1 0 5 - -
events_highpri 8 0 0.0 0 0 - -
events_long 3 0 0.0 0 0 - -
events_unbound 38306 0 0.1 - 7 - -
events_freezable 0 0 0.0 0 0 - -
events_power_efficient 29598 0 0.2 0 0 - -
events_freezable_power_ 10 0 0.0 0 0 - -
sock_diag_events 0 0 0.0 0 0 - -
total infl CPUtime CPUhog CMW/RPR mayday rescued
events 18548 0 6.1 0 5 - -
events_highpri 8 0 0.0 0 0 - -
events_long 3 0 0.0 0 0 - -
events_unbound 38322 0 0.1 - 7 - -
events_freezable 0 0 0.0 0 0 - -
events_power_efficient 29603 0 0.2 0 0 - -
events_freezable_power_ 10 0 0.0 0 0 - -
sock_diag_events 0 0 0.0 0 0 - -
...
参见命令的帮助消息以获取更多信息。
调试
====
@ -330,7 +675,6 @@ And with cmwq with ``@max_active`` >= 3, ::
工作队列保证，如果在工作项排队后满足以下条件，则工作项不能重入：
1. 工作函数没有被改变。
2. 没有人将该工作项排到另一个工作队列中。
3. 该工作项尚未被重新启动。

31
MAINTAINERS
View File

@ -553,7 +553,7 @@ F: Documentation/devicetree/bindings/iio/accel/adi,adxl345.yaml
F: drivers/input/misc/adxl34x.c
ADXL355 THREE-AXIS DIGITAL ACCELEROMETER DRIVER
M: Puranjay Mohan <puranjay12@gmail.com>
M: Puranjay Mohan <puranjay@kernel.org>
L: linux-iio@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/iio/accel/adi,adxl355.yaml
@ -3714,7 +3714,7 @@ F: drivers/iio/imu/bmi323/
BPF JIT for ARM
M: Russell King <linux@armlinux.org.uk>
M: Puranjay Mohan <puranjay12@gmail.com>
M: Puranjay Mohan <puranjay@kernel.org>
L: bpf@vger.kernel.org
S: Maintained
F: arch/arm/net/
@ -3764,6 +3764,8 @@ X: arch/riscv/net/bpf_jit_comp64.c
BPF JIT for RISC-V (64-bit)
M: Björn Töpel <bjorn@kernel.org>
R: Pu Lehui <pulehui@huawei.com>
R: Puranjay Mohan <puranjay@kernel.org>
L: bpf@vger.kernel.org
S: Maintained
F: arch/riscv/net/
@ -4199,7 +4201,6 @@ S: Supported
F: drivers/scsi/bnx2i/
BROADCOM BNX2X 10 GIGABIT ETHERNET DRIVER
M: Ariel Elior <aelior@marvell.com>
M: Sudarsana Kalluru <skalluru@marvell.com>
M: Manish Chopra <manishc@marvell.com>
L: netdev@vger.kernel.org
@ -15190,9 +15191,8 @@ F: drivers/scsi/myrb.*
F: drivers/scsi/myrs.*
MYRICOM MYRI-10G 10GbE DRIVER (MYRI10GE)
M: Chris Lee <christopher.lee@cspi.com>
L: netdev@vger.kernel.org
S: Supported
S: Orphan
W: https://www.cspi.com/ethernet-products/support/downloads/
F: drivers/net/ethernet/myricom/myri10ge/
@ -16829,12 +16829,6 @@ S: Maintained
F: drivers/leds/leds-pca9532.c
F: include/linux/leds-pca9532.h
PCA9541 I2C BUS MASTER SELECTOR DRIVER
M: Guenter Roeck <linux@roeck-us.net>
L: linux-i2c@vger.kernel.org
S: Maintained
F: drivers/i2c/muxes/i2c-mux-pca9541.c
PCI DRIVER FOR AARDVARK (Marvell Armada 3700)
M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
M: Pali Rohár <pali@kernel.org>
@ -17911,7 +17905,7 @@ F: Documentation/devicetree/bindings/leds/irled/pwm-ir-tx.yaml
F: drivers/media/rc/pwm-ir-tx.c
PWM SUBSYSTEM
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
M: Uwe Kleine-König <ukleinek@kernel.org>
L: linux-pwm@vger.kernel.org
S: Maintained
Q: https://patchwork.ozlabs.org/project/linux-pwm/list/
@ -18035,7 +18029,6 @@ S: Supported
F: drivers/scsi/qedi/
QLOGIC QL4xxx ETHERNET DRIVER
M: Ariel Elior <aelior@marvell.com>
M: Manish Chopra <manishc@marvell.com>
L: netdev@vger.kernel.org
S: Supported
@ -18045,7 +18038,6 @@ F: include/linux/qed/
QLOGIC QL4xxx RDMA DRIVER
M: Michal Kalderon <mkalderon@marvell.com>
M: Ariel Elior <aelior@marvell.com>
L: linux-rdma@vger.kernel.org
S: Supported
F: drivers/infiniband/hw/qedr/
@ -20215,7 +20207,6 @@ F: include/linux/platform_data/simplefb.h
SIOX
M: Thorsten Scherer <t.scherer@eckelmann.de>
M: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
R: Pengutronix Kernel Team <kernel@pengutronix.de>
S: Supported
F: drivers/gpio/gpio-siox.c
@ -21965,7 +21956,7 @@ F: include/linux/soc/ti/ti_sci_inta_msi.h
F: include/linux/soc/ti/ti_sci_protocol.h
TEXAS INSTRUMENTS' TMP117 TEMPERATURE SENSOR DRIVER
M: Puranjay Mohan <puranjay12@gmail.com>
M: Puranjay Mohan <puranjay@kernel.org>
L: linux-iio@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml
@ -24507,6 +24498,14 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git for-next/har
F: Documentation/admin-guide/LSM/Yama.rst
F: security/yama/
YAML NETLINK (YNL)
M: Donald Hunter <donald.hunter@gmail.com>
M: Jakub Kicinski <kuba@kernel.org>
F: Documentation/netlink/
F: Documentation/userspace-api/netlink/intro-specs.rst
F: Documentation/userspace-api/netlink/specs.rst
F: tools/net/ynl/
YEALINK PHONE DRIVER
M: Henk Vergonet <Henk.Vergonet@gmail.com>
L: usbb2k-api-dev@nongnu.org

2
Makefile
View File

@ -2,7 +2,7 @@
VERSION = 6
PATCHLEVEL = 9
SUBLEVEL = 0
EXTRAVERSION = -rc5
EXTRAVERSION = -rc6
NAME = Hurr durr I'ma ninja sloth
# *DOCUMENTATION*

8
arch/Kconfig
View File

@ -9,6 +9,14 @@
#
source "arch/$(SRCARCH)/Kconfig"
config ARCH_CONFIGURES_CPU_MITIGATIONS
bool
if !ARCH_CONFIGURES_CPU_MITIGATIONS
config CPU_MITIGATIONS
def_bool y
endif
menu "General architecture-dependent options"
config ARCH_HAS_SUBPAGE_FAULTS

1
arch/arc/Kconfig
View File

@ -6,7 +6,6 @@
config ARC
def_bool y
select ARC_TIMERS
select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CACHE_LINE_SIZE
select ARCH_HAS_DEBUG_VM_PGTABLE
select ARCH_HAS_DMA_PREP_COHERENT

4
arch/arc/boot/Makefile
View File

@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
# uImage build relies on mkimage being availble on your host for ARC target
# uImage build relies on mkimage being available on your host for ARC target
# You will need to build u-boot for ARC, rename mkimage to arc-elf32-mkimage
# and make sure it's reacable from your PATH
# and make sure it's reachable from your PATH
OBJCOPYFLAGS= -O binary -R .note -R .note.gnu.build-id -R .comment -S

4
arch/arc/boot/dts/axc003.dtsi
View File

@ -119,9 +119,9 @@ mmc@15000 {
/*
* The DW APB ICTL intc on MB is connected to CPU intc via a
* DT "invisible" DW APB GPIO block, configured to simply pass thru
* interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
* interrupts - setup accordingly in platform init (plat-axs10x/ax10x.c)
*
* So here we mimic a direct connection betwen them, ignoring the
* So here we mimic a direct connection between them, ignoring the
* ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
* instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*

1
arch/arc/boot/dts/hsdk.dts
View File

@ -205,7 +205,6 @@ dmac_cfg_clk: dmac-gpu-cfg-clk {
};
gmac: ethernet@8000 {
#interrupt-cells = <1>;
compatible = "snps,dwmac";
reg = <0x8000 0x2000>;
interrupts = <10>;

2
arch/arc/boot/dts/vdk_axs10x_mb.dtsi
View File

@ -113,7 +113,7 @@ mmc@15000 {
/*
* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
*
* This node is intentionally put outside of MB above becase
* This node is intentionally put outside of MB above because
* it maps areas outside of MB's 0xez-0xfz.
*/
uio_ev: uio@d0000000 {

9
arch/arc/include/asm/cachetype.h
View File

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_ARC_CACHETYPE_H
#define __ASM_ARC_CACHETYPE_H
#include <linux/types.h>
#define cpu_dcache_is_aliasing() true
#endif

2
arch/arc/include/asm/dsp.h
View File

@ -12,7 +12,7 @@
/*
* DSP-related saved registers - need to be saved only when you are
* scheduled out.
* structure fields name must correspond to aux register defenitions for
* structure fields name must correspond to aux register definitions for
* automatic offset calculation in DSP_AUX_SAVE_RESTORE macros
*/
struct dsp_callee_regs {

10
arch/arc/include/asm/entry-compact.h
View File

@ -7,7 +7,7 @@
* Stack switching code can no longer reliably rely on the fact that
* if we are NOT in user mode, stack is switched to kernel mode.
* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
* it's prologue including stack switching from user mode
* its prologue including stack switching from user mode
*
* Vineetg: Aug 28th 2008: Bug #94984
* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
@ -143,7 +143,7 @@
* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
* 3. But before it could switch SP from USER to KERNEL stack
* a L2 IRQ "Interrupts" L1
* Thay way although L2 IRQ happened in Kernel mode, stack is still
* That way although L2 IRQ happened in Kernel mode, stack is still
* not switched.
* To handle this, we may need to switch stack even if in kernel mode
* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
@ -173,7 +173,7 @@
GET_CURR_TASK_ON_CPU r9
/* With current tsk in r9, get it's kernel mode stack base */
/* With current tsk in r9, get its kernel mode stack base */
GET_TSK_STACK_BASE r9, r9
/* save U mode SP @ pt_regs->sp */
@ -282,7 +282,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
* for memory load operations. If used in that way interrupts are deffered
* for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro EXCEPTION_EPILOGUE
@ -350,7 +350,7 @@
* NOTE:
*
* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
* for memory load operations. If used in that way interrupts are deffered
* for memory load operations. If used in that way interrupts are deferred
* by hardware and that is not good.
*-------------------------------------------------------------*/
.macro INTERRUPT_EPILOGUE LVL

4
arch/arc/include/asm/entry.h
View File

@ -7,7 +7,7 @@
#ifndef __ASM_ARC_ENTRY_H
#define __ASM_ARC_ENTRY_H
#include <asm/unistd.h> /* For NR_syscalls defination */
#include <asm/unistd.h> /* For NR_syscalls definition */
#include <asm/arcregs.h>
#include <asm/ptrace.h>
#include <asm/processor.h> /* For VMALLOC_START */
@ -56,7 +56,7 @@
.endm
/*-------------------------------------------------------------
* given a tsk struct, get to the base of it's kernel mode stack
* given a tsk struct, get to the base of its kernel mode stack
* tsk->thread_info is really a PAGE, whose bottom hoists stack
* which grows upwards towards thread_info
*------------------------------------------------------------*/

2
arch/arc/include/asm/irq.h
View File

@ -10,7 +10,7 @@
* ARCv2 can support 240 interrupts in the core interrupts controllers and
* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
* configurations of boards.
* This doesnt affect ARCompact, but we change it to same value
* This doesn't affect ARCompact, but we change it to same value
*/
#define NR_IRQS 512

2
arch/arc/include/asm/irqflags-compact.h
View File

@ -46,7 +46,7 @@
* IRQ Control Macros
*
* All of them have "memory" clobber (compiler barrier) which is needed to
* ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
* ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
*
* Noted at the time of Abilis Timer List corruption

2
arch/arc/include/asm/mmu_context.h
View File

@ -165,7 +165,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* for retiring-mm. However destroy_context( ) still needs to do that because
* between mm_release( ) = >deactive_mm( ) and
* mmput => .. => __mmdrop( ) => destroy_context( )
* there is a good chance that task gets sched-out/in, making it's ASID valid
* there is a good chance that task gets sched-out/in, making its ASID valid
* again (this teased me for a whole day).
*/

2
arch/arc/include/asm/pgtable-bits-arcv2.h
View File

@ -66,7 +66,7 @@
* Other rules which cause the divergence from 1:1 mapping
*
* 1. Although ARC700 can do exclusive execute/write protection (meaning R
* can be tracked independet of X/W unlike some other CPUs), still to
* can be tracked independently of X/W unlike some other CPUs), still to
* keep things consistent with other archs:
* -Write implies Read: W => R
* -Execute implies Read: X => R

2
arch/arc/include/asm/ptrace.h
View File

@ -169,7 +169,7 @@ static inline unsigned long regs_get_register(struct pt_regs *regs,
return *(unsigned long *)((unsigned long)regs + offset);
}
extern int syscall_trace_entry(struct pt_regs *);
extern int syscall_trace_enter(struct pt_regs *);
extern void syscall_trace_exit(struct pt_regs *);
#endif /* !__ASSEMBLY__ */

2
arch/arc/include/asm/shmparam.h
View File

@ -6,7 +6,7 @@
#ifndef __ARC_ASM_SHMPARAM_H
#define __ARC_ASM_SHMPARAM_H
/* Handle upto 2 cache bins */
/* Handle up to 2 cache bins */
#define SHMLBA (2 * PAGE_SIZE)
/* Enforce SHMLBA in shmat */

4
arch/arc/include/asm/smp.h
View File

@ -77,7 +77,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
/*
* ARC700 doesn't support atomic Read-Modify-Write ops.
* Originally Interrupts had to be disabled around code to gaurantee atomicity.
* Originally Interrupts had to be disabled around code to guarantee atomicity.
* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
* based on retry-if-irq-in-atomic (with hardware assist).
* However despite these, we provide the IRQ disabling variant
@ -86,7 +86,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
* support needed.
*
* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
* gaurantted by the platform (not something which core handles).
* guaranteed by the platform (not something which core handles).
* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
* disabling for atomicity.
*

2
arch/arc/include/asm/thread_info.h
View File

@ -38,7 +38,7 @@
struct thread_info {
unsigned long flags; /* low level flags */
unsigned long ksp; /* kernel mode stack top in __switch_to */
int preempt_count; /* 0 => preemptable, <0 => BUG */
int preempt_count; /* 0 => preemptible, <0 => BUG */
int cpu; /* current CPU */
unsigned long thr_ptr; /* TLS ptr */
struct task_struct *task; /* main task structure */

2
arch/arc/include/uapi/asm/swab.h
View File

@ -62,7 +62,7 @@
* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
*
* Joern suggested a better "C" algorithm which is great since
* (1) It is portable to any architecure
* (1) It is portable to any architecture
* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
*/

8
arch/arc/kernel/entry-arcv2.S
View File

@ -5,7 +5,7 @@
* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
*/
#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
#include <linux/linkage.h> /* ARC_{ENTRY,EXIT} */
#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
#include <asm/errno.h>
#include <asm/arcregs.h>
@ -31,7 +31,7 @@ VECTOR res_service ; Reset Vector
VECTOR mem_service ; Mem exception
VECTOR instr_service ; Instrn Error
VECTOR EV_MachineCheck ; Fatal Machine check
VECTOR EV_TLBMissI ; Intruction TLB miss
VECTOR EV_TLBMissI ; Instruction TLB miss
VECTOR EV_TLBMissD ; Data TLB miss
VECTOR EV_TLBProtV ; Protection Violation
VECTOR EV_PrivilegeV ; Privilege Violation
@ -76,11 +76,11 @@ ENTRY(handle_interrupt)
# query in hard ISR path would return false (since .IE is set) which would
# trips genirq interrupt handling asserts.
#
# So do a "soft" disable of interrutps here.
# So do a "soft" disable of interrupts here.
#
# Note this disable is only for consistent book-keeping as further interrupts
# will be disabled anyways even w/o this. Hardware tracks active interrupts
# seperately in AUX_IRQ_ACT.active and will not take new interrupts
# separately in AUX_IRQ_ACT.active and will not take new interrupts
# unless this one returns (or higher prio becomes pending in 2-prio scheme)
IRQ_DISABLE

4
arch/arc/kernel/entry.S
View File

@ -95,7 +95,7 @@ ENTRY(EV_MachineCheck)
lr r0, [efa]
mov r1, sp
; MC excpetions disable MMU
; MC exceptions disable MMU
ARC_MMU_REENABLE r3
lsr r3, r10, 8
@ -209,7 +209,7 @@ trap_with_param:
; ---------------------------------------------
; syscall TRAP
; ABI: (r0-r7) upto 8 args, (r8) syscall number
; ABI: (r0-r7) up to 8 args, (r8) syscall number
; ---------------------------------------------
ENTRY(EV_Trap)

2
arch/arc/kernel/head.S
View File

@ -165,7 +165,7 @@ ENTRY(first_lines_of_secondary)
; setup stack (fp, sp)
mov fp, 0
; set it's stack base to tsk->thread_info bottom
; set its stack base to tsk->thread_info bottom
GET_TSK_STACK_BASE r0, sp
j start_kernel_secondary

2
arch/arc/kernel/intc-arcv2.c
View File

@ -56,7 +56,7 @@ void arc_init_IRQ(void)
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
/*
* ARCv2 core intc provides multiple interrupt priorities (upto 16).
* ARCv2 core intc provides multiple interrupt priorities (up to 16).
* Typical builds though have only two levels (0-high, 1-low)
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
* NMI style interrupts in future (say perf)

7
arch/arc/kernel/kprobes.c
View File

@ -190,7 +190,8 @@ static void __kprobes setup_singlestep(struct kprobe *p, struct pt_regs *regs)
}
}
int __kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
static int
__kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
{
struct kprobe *p;
struct kprobe_ctlblk *kcb;
@ -241,8 +242,8 @@ int __kprobes arc_kprobe_handler(unsigned long addr, struct pt_regs *regs)
return 0;
}
static int __kprobes arc_post_kprobe_handler(unsigned long addr,
struct pt_regs *regs)
static int
__kprobes arc_post_kprobe_handler(unsigned long addr, struct pt_regs *regs)
{
struct kprobe *cur = kprobe_running();
struct kprobe_ctlblk *kcb = get_kprobe_ctlblk();

2
arch/arc/kernel/perf_event.c
View File

@ -38,7 +38,7 @@
* (based on a specific RTL build)
* Below is the static map between perf generic/arc specific event_id and
* h/w condition names.
* At the time of probe, we loop thru each index and find it's name to
* At the time of probe, we loop thru each index and find its name to
* complete the mapping of perf event_id to h/w index as latter is needed
* to program the counter really
*/

2
arch/arc/kernel/setup.c
View File

@ -390,7 +390,7 @@ static void arc_chk_core_config(struct cpuinfo_arc *info)
#ifdef CONFIG_ARC_HAS_DCCM
/*
* DCCM can be arbit placed in hardware.
* Make sure it's placement/sz matches what Linux is built with
* Make sure its placement/sz matches what Linux is built with
*/
if ((unsigned int)__arc_dccm_base != info->dccm.base)
panic("Linux built with incorrect DCCM Base address\n");

7
arch/arc/kernel/signal.c
View File

@ -8,15 +8,16 @@
*
* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
* -do_signal() supports TIF_RESTORE_SIGMASK
* -do_signal() no loner needs oldset, required by OLD sys_sigsuspend
* -sys_rt_sigsuspend() now comes from generic code, so discard arch implemen
* -do_signal() no longer needs oldset, required by OLD sys_sigsuspend
* -sys_rt_sigsuspend() now comes from generic code, so discard arch
* implementation
* -sys_sigsuspend() no longer needs to fudge ptregs, hence that arg removed
* -sys_sigsuspend() no longer loops for do_signal(), sets TIF_xxx and leaves
* the job to do_signal()
*
* vineetg: July 2009
* -Modified Code to support the uClibc provided userland sigreturn stub
* to avoid kernel synthesing it on user stack at runtime, costing TLB
* to avoid kernel synthesizing it on user stack at runtime, costing TLB
* probes and Cache line flushes.
*
* vineetg: July 2009

2
arch/arc/kernel/traps.c
View File

@ -89,7 +89,7 @@ int do_misaligned_access(unsigned long address, struct pt_regs *regs,
/*
* Entry point for miscll errors such as Nested Exceptions
* -Duplicate TLB entry is handled seperately though
* -Duplicate TLB entry is handled separately though
*/
void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
{

4
arch/arc/kernel/vmlinux.lds.S
View File

@ -41,8 +41,8 @@ SECTIONS
#endif
/*
* The reason for having a seperate subsection .init.ramfs is to
* prevent objump from including it in kernel dumps
* The reason for having a separate subsection .init.ramfs is to
* prevent objdump from including it in kernel dumps
*
* Reason for having .init.ramfs above .init is to make sure that the
* binary blob is tucked away to one side, reducing the displacement

4
arch/arc/mm/tlb.c
View File

@ -212,7 +212,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long flags;
/* If range @start to @end is more than 32 TLB entries deep,
* its better to move to a new ASID rather than searching for
* it's better to move to a new ASID rather than searching for
* individual entries and then shooting them down
*
* The calc above is rough, doesn't account for unaligned parts,
@ -408,7 +408,7 @@ static void create_tlb(struct vm_area_struct *vma, unsigned long vaddr, pte_t *p
* -More importantly it makes this handler inconsistent with fast-path
* TLB Refill handler which always deals with "current"
*
* Lets see the use cases when current->mm != vma->mm and we land here
* Let's see the use cases when current->mm != vma->mm and we land here
* 1. execve->copy_strings()->__get_user_pages->handle_mm_fault
* Here VM wants to pre-install a TLB entry for user stack while
* current->mm still points to pre-execve mm (hence the condition).

8
arch/arc/mm/tlbex.S
View File

@ -5,19 +5,19 @@
* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
*
* Vineetg: April 2011 :
* -MMU v1: moved out legacy code into a seperate file
* -MMU v1: moved out legacy code into a separate file
* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
* helps avoid a shift when preparing PD0 from PTE
*
* Vineetg: July 2009
* -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
* entry, so that it doesn't knock out it's I-TLB entry
* -For MMU V2, we need not do heuristics at the time of committing a D-TLB
* entry, so that it doesn't knock out its I-TLB entry
* -Some more fine tuning:
* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
*
* Vineetg: July 2009
* -Practically rewrote the I/D TLB Miss handlers
* Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
* Now 40 and 135 instructions apiece as compared to 131 and 449 resp.
* Hence Leaner by 1.5 K
* Used Conditional arithmetic to replace excessive branching
* Also used short instructions wherever possible

8
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
View File

@ -242,7 +242,7 @@ vddcore: VDD_CORE {
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>;
regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@ -263,7 +263,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>;
regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@ -280,7 +280,7 @@ vldo1: LDO1 {
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@ -296,7 +296,7 @@ vldo2: LDO2 {
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <3300000>;
regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend;
};

8
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
View File

@ -293,7 +293,7 @@ vddcore: VDD_CORE {
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>;
regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>;
};
@ -314,7 +314,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby {
regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>;
regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>;
};
@ -331,7 +331,7 @@ vldo1: LDO1 {
regulator-always-on;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};
@ -346,7 +346,7 @@ vldo2: LDO2 {
regulator-max-microvolt = <3700000>;
regulator-state-standby {
regulator-suspend-voltage = <1800000>;
regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend;
};

1
arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
View File

@ -805,6 +805,7 @@ &usbotg1 {
&pinctrl_usb_pwr>;
dr_mode = "host";
power-active-high;
over-current-active-low;
disable-over-current;
status = "okay";
};

56
arch/arm/net/bpf_jit_32.c
View File

@ -871,16 +871,11 @@ static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
}
/* dst = src (4 bytes)*/
static inline void emit_a32_mov_r(const s8 dst, const s8 src, const u8 off,
struct jit_ctx *ctx) {
static inline void emit_a32_mov_r(const s8 dst, const s8 src, struct jit_ctx *ctx) {
const s8 *tmp = bpf2a32[TMP_REG_1];
s8 rt;
rt = arm_bpf_get_reg32(src, tmp[0], ctx);
if (off && off != 32) {
emit(ARM_LSL_I(rt, rt, 32 - off), ctx);
emit(ARM_ASR_I(rt, rt, 32 - off), ctx);
}
arm_bpf_put_reg32(dst, rt, ctx);
}
@ -889,15 +884,15 @@ static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
const s8 src[],
struct jit_ctx *ctx) {
if (!is64) {
emit_a32_mov_r(dst_lo, src_lo, 0, ctx);
emit_a32_mov_r(dst_lo, src_lo, ctx);
if (!ctx->prog->aux->verifier_zext)
/* Zero out high 4 bytes */
emit_a32_mov_i(dst_hi, 0, ctx);
} else if (__LINUX_ARM_ARCH__ < 6 &&
ctx->cpu_architecture < CPU_ARCH_ARMv5TE) {
/* complete 8 byte move */
emit_a32_mov_r(dst_lo, src_lo, 0, ctx);
emit_a32_mov_r(dst_hi, src_hi, 0, ctx);
emit_a32_mov_r(dst_lo, src_lo, ctx);
emit_a32_mov_r(dst_hi, src_hi, ctx);
} else if (is_stacked(src_lo) && is_stacked(dst_lo)) {
const u8 *tmp = bpf2a32[TMP_REG_1];
@ -917,17 +912,52 @@ static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
static inline void emit_a32_movsx_r64(const bool is64, const u8 off, const s8 dst[], const s8 src[],
struct jit_ctx *ctx) {
const s8 *tmp = bpf2a32[TMP_REG_1];
const s8 *rt;
s8 rs;
s8 rd;
rt = arm_bpf_get_reg64(dst, tmp, ctx);
if (is_stacked(dst_lo))
rd = tmp[1];
else
rd = dst_lo;
rs = arm_bpf_get_reg32(src_lo, rd, ctx);
/* rs may be one of src[1], dst[1], or tmp[1] */
/* Sign extend rs if needed. If off == 32, lower 32-bits of src are moved to dst and sign
* extension only happens in the upper 64 bits.
*/
if (off != 32) {
/* Sign extend rs into rd */
emit(ARM_LSL_I(rd, rs, 32 - off), ctx);
emit(ARM_ASR_I(rd, rd, 32 - off), ctx);
} else {
rd = rs;
}
/* Write rd to dst_lo
*
* Optimization:
* Assume:
* 1. dst == src and stacked.
* 2. off == 32
*
* In this case src_lo was loaded into rd(tmp[1]) but rd was not sign extended as off==32.
* So, we don't need to write rd back to dst_lo as they have the same value.
* This saves us one str instruction.
*/
if (dst_lo != src_lo || off != 32)
arm_bpf_put_reg32(dst_lo, rd, ctx);
emit_a32_mov_r(dst_lo, src_lo, off, ctx);
if (!is64) {
if (!ctx->prog->aux->verifier_zext)
/* Zero out high 4 bytes */
emit_a32_mov_i(dst_hi, 0, ctx);
} else {
emit(ARM_ASR_I(rt[0], rt[1], 31), ctx);
if (is_stacked(dst_hi)) {
emit(ARM_ASR_I(tmp[0], rd, 31), ctx);
arm_bpf_put_reg32(dst_hi, tmp[0], ctx);
} else {
emit(ARM_ASR_I(dst_hi, rd, 31), ctx);
}
}
}

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1672,7 +1672,7 @@ mipi_csi_1: csi@32e50000 {
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>;

8
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View File

@ -129,7 +129,7 @@ ethernet_phy0: ethernet-phy@5 {
};
&pio {
eth_default: eth_default {
eth_default: eth-default-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
@ -156,7 +156,7 @@ mdio_pins {
};
};
eth_sleep: eth_sleep {
eth_sleep: eth-sleep-pins {
tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
@ -182,14 +182,14 @@ mdio_pins {
};
};
usb0_id_pins_float: usb0_iddig {
usb0_id_pins_float: usb0-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up;
};
};
usb1_id_pins_float: usb1_iddig {
usb1_id_pins_float: usb1-iddig-pins {
pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up;

3
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View File

@ -249,10 +249,11 @@ topckgen: syscon@10000000 {
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
infracfg: clock-controller@10001000 {
compatible = "mediatek,mt2712-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pericfg: syscon@10003000 {

34
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View File

@ -252,7 +252,7 @@ scpsys: power-controller@10006000 {
clock-names = "hif_sel";
};
cir: cir@10009000 {
cir: ir-receiver@10009000 {
compatible = "mediatek,mt7622-cir";
reg = <0 0x10009000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@ -283,16 +283,14 @@ thermal_calibration: calib@198 {
};
};
apmixedsys: apmixedsys@10209000 {
compatible = "mediatek,mt7622-apmixedsys",
"syscon";
apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt7622-apmixedsys";
reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@10210000 {
compatible = "mediatek,mt7622-topckgen",
"syscon";
topckgen: clock-controller@10210000 {
compatible = "mediatek,mt7622-topckgen";
reg = <0 0x10210000 0 0x1000>;
#clock-cells = <1>;
};
@ -515,7 +513,6 @@ thermal: thermal@1100b000 {
<&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "therm", "auxadc";
resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
reset-names = "therm";
mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>;
@ -734,9 +731,8 @@ wmac: wmac@18000000 {
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
};
ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys",
"syscon";
ssusbsys: clock-controller@1a000000 {
compatible = "mediatek,mt7622-ssusbsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -793,9 +789,8 @@ u2port1: usb-phy@1a0c5000 {
};
};
pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys",
"syscon";
pciesys: clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
@ -921,12 +916,13 @@ sata_port: sata-phy@1a243000 {
};
};
hifsys: syscon@1af00000 {
compatible = "mediatek,mt7622-hifsys", "syscon";
hifsys: clock-controller@1af00000 {
compatible = "mediatek,mt7622-hifsys";
reg = <0 0x1af00000 0 0x70>;
#clock-cells = <1>;
};
ethsys: syscon@1b000000 {
ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt7622-ethsys",
"syscon";
reg = <0 0x1b000000 0 0x1000>;
@ -966,9 +962,7 @@ wed1: wed@1020b000 {
};
eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth",
"mediatek,mt2701-eth",
"syscon";
compatible = "mediatek,mt7622-eth";
reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,

6
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View File

@ -146,19 +146,19 @@ sfp2: sfp-2 {
&cpu_thermal {
cooling-maps {
cpu-active-high {
map-cpu-active-high {
/* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>;
};
cpu-active-med {
map-cpu-active-med {
/* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>;
};
cpu-active-low {
map-cpu-active-low {
/* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>;

8
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@ -332,9 +332,8 @@ thermal: thermal@1100c800 {
reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>,
<&infracfg CLK_INFRA_ADC_FRC_CK>;
clock-names = "therm", "auxadc", "adc_32k";
<&infracfg CLK_INFRA_ADC_26M_CK>;
clock-names = "therm", "auxadc";
nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>;
@ -492,8 +491,6 @@ ethsys: syscon@15000000 {
compatible = "mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -556,7 +553,6 @@ eth: ethernet@15100000 {
<&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
mediatek,ethsys = <&ethsys>;

1
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -433,7 +433,6 @@ &mt6358regulator {
};
&mt6358_vgpu_reg {
regulator-min-microvolt = <625000>;
regulator-max-microvolt = <900000>;
regulator-coupled-with = <&mt6358_vsram_gpu_reg>;

1
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1637,6 +1637,7 @@ mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
gpu: gpu@13040000 {

2
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
View File

@ -1296,7 +1296,7 @@ mt6366_vgpu_reg: vgpu {
* regulator coupling requirements.
*/
regulator-name = "ppvar_dvdd_vgpu";
regulator-min-microvolt = <600000>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>;

6
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@ -1421,7 +1421,7 @@ regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
@ -1431,7 +1431,7 @@ mt6315_6_vbuck1: vbuck1 {
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;
@ -1448,7 +1448,7 @@ regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <606250>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>;

1
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@ -1464,6 +1464,7 @@ mutex: mutex@14001000 {
reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;

36
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -264,6 +264,38 @@ &auxadc {
status = "okay";
};
&cpu0 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu1 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu2 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu3 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu4 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu5 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu6 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu7 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&dp_intf0 {
status = "okay";
@ -1214,7 +1246,7 @@ regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;
@ -1232,7 +1264,7 @@ regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <625000>;
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>;

5
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -2028,6 +2028,7 @@ vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
};
dma-controller@14001000 {
@ -2251,6 +2252,7 @@ vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
};
mutex@14f01000 {
@ -3080,6 +3082,7 @@ vdosys0: syscon@1c01a000 {
reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
};
@ -3261,6 +3264,7 @@ mutex: mutex@1c016000 {
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
};
@ -3331,6 +3335,7 @@ mutex1: mutex@1c101000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
clock-names = "vdo1_mutex";
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
};

4
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -3707,7 +3707,7 @@ remoteproc_adsp: remoteproc@3700000 {
compatible = "qcom,sc7280-adsp-pas";
reg = <0 0x03700000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@ -3944,7 +3944,7 @@ remoteproc_cdsp: remoteproc@a300000 {
compatible = "qcom,sc7280-cdsp-pas";
reg = <0 0x0a300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,

2
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View File

@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",

11
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -1774,6 +1774,7 @@ pcie4: pcie@1c00000 {
reset-names = "pci";
power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>;
phy-names = "pciephy";
@ -1872,6 +1873,7 @@ pcie3b: pcie@1c08000 {
reset-names = "pci";
power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3b_phy>;
phy-names = "pciephy";
@ -1970,6 +1972,7 @@ pcie3a: pcie@1c10000 {
reset-names = "pci";
power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3a_phy>;
phy-names = "pciephy";
@ -2071,6 +2074,7 @@ pcie2b: pcie@1c18000 {
reset-names = "pci";
power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2b_phy>;
phy-names = "pciephy";
@ -2169,6 +2173,7 @@ pcie2a: pcie@1c20000 {
reset-names = "pci";
power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2a_phy>;
phy-names = "pciephy";
@ -2641,7 +2646,7 @@ remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
@ -4977,7 +4982,7 @@ remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
@ -5108,7 +5113,7 @@ remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,

4
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@ -1252,7 +1252,7 @@ adsp: remoteproc@3000000 {
compatible = "qcom,sm6350-adsp-pas";
reg = <0 0x03000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
@ -1511,7 +1511,7 @@ cdsp: remoteproc@8300000 {
compatible = "qcom,sm6350-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,

2
arch/arm64/boot/dts/qcom/sm6375.dtsi
View File

@ -1561,7 +1561,7 @@ remoteproc_adsp: remoteproc@a400000 {
compatible = "qcom,sm6375-adsp-pas";
reg = <0 0x0a400000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,

6
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -3062,7 +3062,7 @@ slpi: remoteproc@5c00000 {
compatible = "qcom,sm8250-slpi-pas";
reg = <0 0x05c00000 0 0x4000>;
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
@ -3766,7 +3766,7 @@ cdsp: remoteproc@8300000 {
compatible = "qcom,sm8250-cdsp-pas";
reg = <0 0x08300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
@ -5928,7 +5928,7 @@ adsp: remoteproc@17300000 {
compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x17300000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,

16
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -1777,12 +1777,8 @@ pcie0: pcie@1c00000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
/*
* MSIs for BDF (1:0.0) only works with Device ID 0x5980.
* Hence, the IDs are swapped.
*/
msi-map = <0x0 &gic_its 0x5981 0x1>,
<0x100 &gic_its 0x5980 0x1>;
msi-map = <0x0 &gic_its 0x5980 0x1>,
<0x100 &gic_its 0x5981 0x1>;
msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
@ -1900,12 +1896,8 @@ pcie1: pcie@1c08000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
/*
* MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
* Hence, the IDs are swapped.
*/
msi-map = <0x0 &gic_its 0x5a01 0x1>,
<0x100 &gic_its 0x5a00 0x1>;
msi-map = <0x0 &gic_its 0x5a00 0x1>,
<0x100 &gic_its 0x5a01 0x1>;
msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,

10
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@ -1755,9 +1755,8 @@ pcie0: pcie@1c00000 {
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1401 0x1>,
<0x100 &gic_its 0x1400 0x1>;
msi-map = <0x0 &gic_its 0x1400 0x1>,
<0x100 &gic_its 0x1401 0x1>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
@ -1867,9 +1866,8 @@ pcie1: pcie@1c08000 {
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1481 0x1>,
<0x100 &gic_its 0x1480 0x1>;
msi-map = <0x0 &gic_its 0x1480 0x1>,
<0x100 &gic_its 0x1481 0x1>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>;

10
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@ -2274,9 +2274,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1401 0x1>,
<0x100 &gic_its 0x1400 0x1>;
msi-map = <0x0 &gic_its 0x1400 0x1>,
<0x100 &gic_its 0x1401 0x1>;
msi-map-mask = <0xff00>;
linux,pci-domain = <0>;
@ -2402,9 +2401,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */
msi-map = <0x0 &gic_its 0x1481 0x1>,
<0x100 &gic_its 0x1480 0x1>;
msi-map = <0x0 &gic_its 0x1480 0x1>,
<0x100 &gic_its 0x1481 0x1>;
msi-map-mask = <0xff00>;
linux,pci-domain = <1>;

4
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -284,7 +284,7 @@ CLUSTER_C4: cpu-sleep-0 {
domain-idle-states {
CLUSTER_CL4: cluster-sleep-0 {
compatible = "arm,idle-state";
compatible = "domain-idle-state";
idle-state-name = "l2-ret";
arm,psci-suspend-param = <0x01000044>;
entry-latency-us = <350>;
@ -293,7 +293,7 @@ CLUSTER_CL4: cluster-sleep-0 {
};
CLUSTER_CL5: cluster-sleep-1 {
compatible = "arm,idle-state";
compatible = "domain-idle-state";
idle-state-name = "ret-pll-off";
arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2200>;

3
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View File

@ -663,7 +663,7 @@ mipi_in_panel: endpoint {
port@1 {
reg = <1>;
mipi1_in_panel: endpoint@1 {
mipi1_in_panel: endpoint {
remote-endpoint = <&mipi1_out_panel>;
};
};
@ -689,7 +689,6 @@ &pcie0 {
ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
/* PERST# asserted in S3 */
pcie-reset-suspend = <1>;
vpcie3v3-supply = <&wlan_3v3>;
vpcie1v8-supply = <&pp1800_pcie>;

2
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
View File

@ -611,7 +611,7 @@ device@4 {
#size-cells = <0>;
interface@0 { /* interface 0 of configuration 1 */
compatible = "usbbda,8156.config1.0";
compatible = "usbifbda,8156.config1.0";
reg = <0 1>;
};
};

1
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View File

@ -779,7 +779,6 @@ &pcie_phy {
};
&pcie0 {
bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";

2
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
View File

@ -194,6 +194,8 @@ &pcie0 {
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
vpcie3v3-supply = <&vcc3v3_baseboard>;
vpcie12v-supply = <&dc_12v>;
status = "okay";
};

53
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
View File

@ -79,6 +79,26 @@ vcc5v0_sys: vcc5v0-sys {
regulator-max-microvolt = <5000000>;
};
vcca_0v9: vcca-0v9-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc_1v8>;
};
vcca_1v8: vcca-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys>;
};
vdd_log: vdd-log {
compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>;
@ -416,16 +436,28 @@ &io_domains {
gpio1830-supply = <&vcc_1v8>;
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
&pcie0 {
/* PCIe PHY supplies */
vpcie0v9-supply = <&vcca_0v9>;
vpcie1v8-supply = <&vcca_1v8>;
};
&pwm2 {
status = "okay";
&pcie_clkreqn_cpm {
rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&q7_thermal_pin>;
gpios {
q7_thermal_pin: q7-thermal-pin {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
i2c8 {
i2c8_xfer_a: i2c8-xfer {
rockchip,pins =
@ -458,11 +490,20 @@ vcc5v0_host_en: vcc5v0-host-en {
usb3 {
usb3_id: usb3-id {
rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
};
&pwm2 {
status = "okay";
};
&sdhci {
/*
* Signal integrity isn't great at 200MHz but 100MHz has proven stable

1
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
View File

@ -447,7 +447,6 @@ rgmii_phy1: phy@0 {
&pcie2x1 {
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
};

6
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
View File

@ -416,6 +416,8 @@ regulator-state-mem {
vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -525,9 +527,9 @@ &mdio0 {
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
switch@1f {
compatible = "mediatek,mt7531";
reg = <0>;
reg = <0x1f>;
ports {
#address-cells = <1>;

1
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
View File

@ -523,7 +523,6 @@ &pcie3x2 {
&pcie2x1 {
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_mini_pcie>;
status = "okay";
};

4
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
View File

@ -216,9 +216,9 @@ &i2c7 {
pinctrl-0 = <&i2c7m0_xfer>;
status = "okay";
es8316: audio-codec@11 {
es8316: audio-codec@10 {
compatible = "everest,es8316";
reg = <0x11>;
reg = <0x10>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>;
clocks = <&cru I2S0_8CH_MCLKOUT>;

3
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
View File

@ -485,6 +485,7 @@ pmic@0 {
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
@ -506,7 +507,7 @@ pmic@0 {
#gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl2";
pins = "gpio_pwrctrl1";
function = "pin_fun0";
};

1
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
View File

@ -456,6 +456,7 @@ pmic@0 {
<&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-names = "default";
spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc4v0_sys>;
vcc2-supply = <&vcc4v0_sys>;

8
arch/arm64/kvm/vgic/vgic-kvm-device.c
View File

@ -338,12 +338,12 @@ int kvm_register_vgic_device(unsigned long type)
int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
struct vgic_reg_attr *reg_attr)
{
int cpuid;
int cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr);
cpuid = FIELD_GET(KVM_DEV_ARM_VGIC_CPUID_MASK, attr->attr);
reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid);
reg_attr->addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
reg_attr->vcpu = kvm_get_vcpu_by_id(dev->kvm, cpuid);
if (!reg_attr->vcpu)
return -EINVAL;
return 0;
}

6
arch/arm64/net/bpf_jit_comp.c
View File

@ -1905,15 +1905,15 @@ static void invoke_bpf_prog(struct jit_ctx *ctx, struct bpf_tramp_link *l,
emit_call(enter_prog, ctx);
/* save return value to callee saved register x20 */
emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx);
/* if (__bpf_prog_enter(prog) == 0)
* goto skip_exec_of_prog;
*/
branch = ctx->image + ctx->idx;
emit(A64_NOP, ctx);
/* save return value to callee saved register x20 */
emit(A64_MOV(1, A64_R(20), A64_R(0)), ctx);
emit(A64_ADD_I(1, A64_R(0), A64_SP, args_off), ctx);
if (!p->jited)
emit_addr_mov_i64(A64_R(1), (const u64)p->insnsi, ctx);

2
arch/loongarch/Kconfig
View File

@ -595,7 +595,7 @@ config ARCH_SELECTS_CRASH_DUMP
select RELOCATABLE
config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
def_bool CRASH_CORE
def_bool CRASH_RESERVE
config RELOCATABLE
bool "Relocatable kernel"

4
arch/loongarch/include/asm/crash_core.h → arch/loongarch/include/asm/crash_reserve.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _LOONGARCH_CRASH_CORE_H
#define _LOONGARCH_CRASH_CORE_H
#ifndef _LOONGARCH_CRASH_RESERVE_H
#define _LOONGARCH_CRASH_RESERVE_H
#define CRASH_ALIGN SZ_2M

8
arch/loongarch/include/asm/perf_event.h
View File

@ -7,6 +7,14 @@
#ifndef __LOONGARCH_PERF_EVENT_H__
#define __LOONGARCH_PERF_EVENT_H__
#include <asm/ptrace.h>
#define perf_arch_bpf_user_pt_regs(regs) (struct user_pt_regs *)regs
#define perf_arch_fetch_caller_regs(regs, __ip) { \
(regs)->csr_era = (__ip); \
(regs)->regs[3] = current_stack_pointer; \
(regs)->regs[22] = (unsigned long) __builtin_frame_address(0); \
}
#endif /* __LOONGARCH_PERF_EVENT_H__ */

2
arch/loongarch/include/asm/tlb.h
View File

@ -132,8 +132,6 @@ static __always_inline void invtlb_all(u32 op, u32 info, u64 addr)
);
}
#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
static void tlb_flush(struct mmu_gather *tlb);
#define tlb_flush tlb_flush

2
arch/loongarch/kernel/perf_event.c
View File

@ -884,4 +884,4 @@ static int __init init_hw_perf_events(void)
return 0;
}
early_initcall(init_hw_perf_events);
pure_initcall(init_hw_perf_events);

4
arch/loongarch/mm/fault.c
View File

@ -202,10 +202,10 @@ static void __kprobes __do_page_fault(struct pt_regs *regs,
if (!(vma->vm_flags & VM_WRITE))
goto bad_area;
} else {
if (!(vma->vm_flags & VM_READ) && address != exception_era(regs))
goto bad_area;
if (!(vma->vm_flags & VM_EXEC) && address == exception_era(regs))
goto bad_area;
if (!(vma->vm_flags & (VM_READ | VM_WRITE)) && address != exception_era(regs))
goto bad_area;
}
/*

8
arch/riscv/Kconfig.errata
View File

@ -82,14 +82,14 @@ config ERRATA_THEAD
Otherwise, please say "N" here to avoid unnecessary overhead.
config ERRATA_THEAD_PBMT
bool "Apply T-Head memory type errata"
config ERRATA_THEAD_MAE
bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
depends on ERRATA_THEAD && 64BIT && MMU
select RISCV_ALTERNATIVE_EARLY
default y
help
This will apply the memory type errata to handle the non-standard
memory type bits in page-table-entries on T-Head SoCs.
This will apply the memory attribute extension errata to handle the
non-standard PTE utilization on T-Head SoCs (XTheadMae).
If you don't know what to do here, say "Y".

24
arch/riscv/errata/thead/errata.c
View File

@ -19,20 +19,26 @@
#include <asm/patch.h>
#include <asm/vendorid_list.h>
static bool errata_probe_pbmt(unsigned int stage,
unsigned long arch_id, unsigned long impid)
#define CSR_TH_SXSTATUS 0x5c0
#define SXSTATUS_MAEE _AC(0x200000, UL)
static bool errata_probe_mae(unsigned int stage,
unsigned long arch_id, unsigned long impid)
{
if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT))
if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAE))
return false;
if (arch_id != 0 || impid != 0)
return false;
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT ||
stage == RISCV_ALTERNATIVES_MODULE)
return true;
if (stage != RISCV_ALTERNATIVES_EARLY_BOOT &&
stage != RISCV_ALTERNATIVES_MODULE)
return false;
return false;
if (!(csr_read(CSR_TH_SXSTATUS) & SXSTATUS_MAEE))
return false;
return true;
}
/*
@ -140,8 +146,8 @@ static u32 thead_errata_probe(unsigned int stage,
{
u32 cpu_req_errata = 0;
if (errata_probe_pbmt(stage, archid, impid))
cpu_req_errata |= BIT(ERRATA_THEAD_PBMT);
if (errata_probe_mae(stage, archid, impid))
cpu_req_errata |= BIT(ERRATA_THEAD_MAE);
errata_probe_cmo(stage, archid, impid);

20
arch/riscv/include/asm/errata_list.h
View File

@ -23,7 +23,7 @@
#endif
#ifdef CONFIG_ERRATA_THEAD
#define ERRATA_THEAD_PBMT 0
#define ERRATA_THEAD_MAE 0
#define ERRATA_THEAD_PMU 1
#define ERRATA_THEAD_NUMBER 2
#endif
@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
* in the default case.
*/
#define ALT_SVPBMT_SHIFT 61
#define ALT_THEAD_PBMT_SHIFT 59
#define ALT_THEAD_MAE_SHIFT 59
#define ALT_SVPBMT(_val, prot) \
asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
"li %0, %1\t\nslli %0,%0,%3", 0, \
RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
: "=r"(_val) \
: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
"I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(ALT_SVPBMT_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT))
"I"(ALT_THEAD_MAE_SHIFT))
#ifdef CONFIG_ERRATA_THEAD_PBMT
#ifdef CONFIG_ERRATA_THEAD_MAE
/*
* IO/NOCACHE memory types are handled together with svpbmt,
* so on T-Head chips, check if no other memory type is set,
@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE( \
"slli t3, t3, %3\n\t" \
"or %0, %0, t3\n\t" \
"2:", THEAD_VENDOR_ID, \
ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
: "+r"(_val) \
: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
"I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT) \
: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(ALT_THEAD_MAE_SHIFT) \
: "t3")
#else
#define ALT_THEAD_PMA(_val)

2
arch/riscv/include/asm/page.h
View File

@ -89,7 +89,7 @@ typedef struct page *pgtable_t;
#define PTE_FMT "%08lx"
#endif
#ifdef CONFIG_64BIT
#if defined(CONFIG_64BIT) && defined(CONFIG_MMU)
/*
* We override this value as its generic definition uses __pa too early in
* the boot process (before kernel_map.va_pa_offset is set).

2
arch/riscv/include/asm/pgtable.h
View File

@ -896,7 +896,7 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
#define PAGE_SHARED __pgprot(0)
#define PAGE_KERNEL __pgprot(0)
#define swapper_pg_dir NULL
#define TASK_SIZE 0xffffffffUL
#define TASK_SIZE _AC(-1, UL)
#define VMALLOC_START _AC(0, UL)
#define VMALLOC_END TASK_SIZE

2
arch/riscv/include/uapi/asm/hwprobe.h
View File

@ -54,7 +54,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZFHMIN (1 << 28)
#define RISCV_HWPROBE_EXT_ZIHINTNTL (1 << 29)
#define RISCV_HWPROBE_EXT_ZVFH (1 << 30)
#define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31)
#define RISCV_HWPROBE_EXT_ZVFHMIN (1ULL << 31)
#define RISCV_HWPROBE_EXT_ZFA (1ULL << 32)
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)

2
arch/riscv/mm/init.c
View File

@ -231,7 +231,7 @@ static void __init setup_bootmem(void)
* In 64-bit, any use of __va/__pa before this point is wrong as we
* did not know the start of DRAM before.
*/
if (IS_ENABLED(CONFIG_64BIT))
if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU))
kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
/*

6
arch/riscv/net/bpf_jit_comp64.c
View File

@ -730,6 +730,9 @@ static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_of
if (ret)
return ret;
/* store prog start time */
emit_mv(RV_REG_S1, RV_REG_A0, ctx);
/* if (__bpf_prog_enter(prog) == 0)
* goto skip_exec_of_prog;
*/
@ -737,9 +740,6 @@ static int invoke_bpf_prog(struct bpf_tramp_link *l, int args_off, int retval_of
/* nop reserved for conditional jump */
emit(rv_nop(), ctx);
/* store prog start time */
emit_mv(RV_REG_S1, RV_REG_A0, ctx);
/* arg1: &args_off */
emit_addi(RV_REG_A0, RV_REG_FP, -args_off, ctx);
if (!p->jited)

19
arch/x86/Kconfig
View File

@ -62,6 +62,7 @@ config X86
select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU
select ARCH_32BIT_OFF_T if X86_32
select ARCH_CLOCKSOURCE_INIT
select ARCH_CONFIGURES_CPU_MITIGATIONS
select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
select ARCH_ENABLE_HUGEPAGE_MIGRATION if X86_64 && HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_MEMORY_HOTPLUG if X86_64
@ -2488,17 +2489,21 @@ config PREFIX_SYMBOLS
def_bool y
depends on CALL_PADDING && !CFI_CLANG
menuconfig SPECULATION_MITIGATIONS
bool "Mitigations for speculative execution vulnerabilities"
menuconfig CPU_MITIGATIONS
bool "Mitigations for CPU vulnerabilities"
default y
help
Say Y here to enable options which enable mitigations for
speculative execution hardware vulnerabilities.
Say Y here to enable options which enable mitigations for hardware
vulnerabilities (usually related to speculative execution).
Mitigations can be disabled or restricted to SMT systems at runtime
via the "mitigations" kernel parameter.
If you say N, all mitigations will be disabled. You really
should know what you are doing to say so.
If you say N, all mitigations will be disabled. This CANNOT be
overridden at runtime.
if SPECULATION_MITIGATIONS
Say 'Y', unless you really know what you are doing.
if CPU_MITIGATIONS
config MITIGATION_PAGE_TABLE_ISOLATION
bool "Remove the kernel mapping in user mode"

1
arch/x86/include/asm/coco.h
View File

@ -25,6 +25,7 @@ u64 cc_mkdec(u64 val);
void cc_random_init(void);
#else
#define cc_vendor (CC_VENDOR_NONE)
static const u64 cc_mask = 0;
static inline u64 cc_mkenc(u64 val)
{

3
arch/x86/include/asm/pgtable_types.h
View File

@ -148,7 +148,7 @@
#define _COMMON_PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
_PAGE_SPECIAL | _PAGE_ACCESSED | \
_PAGE_DIRTY_BITS | _PAGE_SOFT_DIRTY | \
_PAGE_DEVMAP | _PAGE_ENC | _PAGE_UFFD_WP)
_PAGE_DEVMAP | _PAGE_CC | _PAGE_UFFD_WP)
#define _PAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PAT)
#define _HPAGE_CHG_MASK (_COMMON_PAGE_CHG_MASK | _PAGE_PSE | _PAGE_PAT_LARGE)
@ -173,6 +173,7 @@ enum page_cache_mode {
};
#endif
#define _PAGE_CC (_AT(pteval_t, cc_mask))
#define _PAGE_ENC (_AT(pteval_t, sme_me_mask))
#define _PAGE_CACHE_MASK (_PAGE_PWT | _PAGE_PCD | _PAGE_PAT)

3
arch/x86/kernel/cpu/amd.c
View File

@ -459,8 +459,7 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
case 0x1a:
switch (c->x86_model) {
case 0x00 ... 0x0f:
case 0x20 ... 0x2f:
case 0x00 ... 0x2f:
case 0x40 ... 0x4f:
case 0x70 ... 0x7f:
setup_force_cpu_cap(X86_FEATURE_ZEN5);

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