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ARM: OMAP1: clock: Remove noop code
There are some OMAP1 clock code bits that have no effect: - crystal_type variable is set to 0 but never changed, then crystal_type == 2 condition is never true and ck_ref.rate never set to 19200000, - clk->ops->allow_idle() is called from omap_clk_enable_autoidle_all() but that op is not configured for any clock, then the function does nothing and the op field is not needed, - ENABLE_ON_INIT flag is set for some clocks but is never checked by any code, then not needed. Drop that code. Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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@ -798,22 +798,6 @@ void clk_unregister(struct clk *clk)
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}
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EXPORT_SYMBOL(clk_unregister);
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int omap_clk_enable_autoidle_all(void)
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{
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struct clk *c;
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unsigned long flags;
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spin_lock_irqsave(&clockfw_lock, flags);
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list_for_each_entry(c, &clocks, node)
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if (c->ops->allow_idle)
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c->ops->allow_idle(c);
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spin_unlock_irqrestore(&clockfw_lock, flags);
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return 0;
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}
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/*
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* Low level helpers
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*/
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@ -871,7 +855,6 @@ static int __init clk_disable_unused(void)
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return 0;
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}
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late_initcall(clk_disable_unused);
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late_initcall(omap_clk_enable_autoidle_all);
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#endif
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
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@ -53,7 +53,6 @@ struct omap_clk {
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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void (*allow_idle)(struct clk *);
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};
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/*
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@ -64,7 +63,6 @@ struct clkops {
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
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#define CLOCK_IDLE_CONTROL (1 << 1)
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#define CLOCK_NO_IDLE_PARENT (1 << 2)
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
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/**
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* struct clk - OMAP struct clk
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@ -135,7 +133,6 @@ extern void clk_unregister(struct clk *clk);
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extern void propagate_rate(struct clk *clk);
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extern unsigned long followparent_recalc(struct clk *clk);
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unsigned long omap_fixed_divisor_recalc(struct clk *clk);
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extern int omap_clk_enable_autoidle_all(void);
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extern const struct clkops clkops_null;
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@ -92,8 +92,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
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.name = "ck_dpll1out",
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
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ENABLE_ON_INIT,
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.flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
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.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
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.enable_bit = EN_CKOUT_ARM,
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.recalc = &followparent_recalc,
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@ -146,7 +145,6 @@ static struct clk arm_gpio_ck = {
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.name = "ick",
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.ops = &clkops_generic,
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.parent = &ck_dpll1,
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.flags = ENABLE_ON_INIT,
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.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
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.enable_bit = EN_GPIOCK,
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.recalc = &followparent_recalc,
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@ -316,7 +314,6 @@ static struct clk tc2_ck = {
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.name = "tc2_ck",
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.ops = &clkops_generic,
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.parent = &tc_ck.clk,
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.flags = ENABLE_ON_INIT,
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.enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
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.enable_bit = EN_TC2_CK,
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.recalc = &followparent_recalc,
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@ -762,7 +759,6 @@ u32 cpu_mask;
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int __init omap1_clk_init(void)
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{
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struct omap_clk *c;
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int crystal_type = 0; /* Default 12 MHz */
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u32 reg;
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#ifdef CONFIG_DEBUG_LL
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@ -810,8 +806,6 @@ int __init omap1_clk_init(void)
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if (cpu_is_omap7xx())
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ck_ref.rate = 13000000;
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if (cpu_is_omap16xx() && crystal_type == 2)
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ck_ref.rate = 19200000;
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pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
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omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
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