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leds: sun50i-a100: New driver for the A100 LED controller
Some Allwinner sunxi SoCs, starting with the A100, contain an LED controller designed to drive RGB LED pixels. Add a driver for it using the multicolor LED framework, and with LEDs defined in the device tree. Acked-by: Guo Ren <guoren@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20231029212738.7871-3-samuel@sholland.org Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Samuel Holland
Lee Jones
parent
65dcdf495a
commit
ec95a68dad
@ -298,6 +298,15 @@ config LEDS_COBALT_RAQ
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help
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This option enables support for the Cobalt Raq series LEDs.
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config LEDS_SUN50I_A100
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tristate "LED support for Allwinner A100 RGB LED controller"
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depends on LEDS_CLASS_MULTICOLOR && OF
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depends on ARCH_SUNXI || COMPILE_TEST
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help
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This option enables support for the RGB LED controller found
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in some Allwinner sunxi SoCs, including A100, R329, and D1.
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It uses a one-wire interface to control up to 1024 LEDs.
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config LEDS_SUNFIRE
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tristate "LED support for SunFire servers."
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depends on LEDS_CLASS
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@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powernv.o
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obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
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obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
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obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
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obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o
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obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
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obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o
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obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o
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580
drivers/leds/leds-sun50i-a100.c
Normal file
580
drivers/leds/leds-sun50i-a100.c
Normal file
@ -0,0 +1,580 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021-2023 Samuel Holland <samuel@sholland.org>
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*
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* Partly based on drivers/leds/leds-turris-omnia.c, which is:
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* Copyright (c) 2020 by Marek Behún <kabel@kernel.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/led-class-multicolor.h>
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#include <linux/leds.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#define LEDC_CTRL_REG 0x0000
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#define LEDC_CTRL_REG_DATA_LENGTH GENMASK(28, 16)
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#define LEDC_CTRL_REG_RGB_MODE GENMASK(8, 6)
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#define LEDC_CTRL_REG_LEDC_EN BIT(0)
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#define LEDC_T01_TIMING_CTRL_REG 0x0004
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#define LEDC_T01_TIMING_CTRL_REG_T1H GENMASK(26, 21)
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#define LEDC_T01_TIMING_CTRL_REG_T1L GENMASK(20, 16)
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#define LEDC_T01_TIMING_CTRL_REG_T0H GENMASK(10, 6)
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#define LEDC_T01_TIMING_CTRL_REG_T0L GENMASK(5, 0)
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#define LEDC_RESET_TIMING_CTRL_REG 0x000c
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#define LEDC_RESET_TIMING_CTRL_REG_TR GENMASK(28, 16)
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#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM GENMASK(9, 0)
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#define LEDC_DATA_REG 0x0014
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#define LEDC_DMA_CTRL_REG 0x0018
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#define LEDC_DMA_CTRL_REG_DMA_EN BIT(5)
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#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL GENMASK(4, 0)
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#define LEDC_INT_CTRL_REG 0x001c
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#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN BIT(5)
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#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN BIT(1)
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#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN BIT(0)
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#define LEDC_INT_STS_REG 0x0020
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#define LEDC_INT_STS_REG_FIFO_WLW GENMASK(15, 10)
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#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT BIT(1)
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#define LEDC_INT_STS_REG_TRANS_FINISH_INT BIT(0)
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#define LEDC_FIFO_DEPTH 32U
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#define LEDC_MAX_LEDS 1024
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#define LEDC_CHANNELS_PER_LED 3 /* RGB */
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#define LEDS_TO_BYTES(n) ((n) * sizeof(u32))
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struct sun50i_a100_ledc_led {
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struct led_classdev_mc mc_cdev;
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struct mc_subled subled_info[LEDC_CHANNELS_PER_LED];
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u32 addr;
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};
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#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)
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struct sun50i_a100_ledc_timing {
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u32 t0h_ns;
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u32 t0l_ns;
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u32 t1h_ns;
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u32 t1l_ns;
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u32 treset_ns;
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};
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struct sun50i_a100_ledc {
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struct device *dev;
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void __iomem *base;
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struct clk *bus_clk;
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struct clk *mod_clk;
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struct reset_control *reset;
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u32 *buffer;
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struct dma_chan *dma_chan;
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dma_addr_t dma_handle;
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unsigned int pio_length;
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unsigned int pio_offset;
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spinlock_t lock;
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unsigned int next_length;
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bool xfer_active;
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u32 format;
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struct sun50i_a100_ledc_timing timing;
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u32 max_addr;
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u32 num_leds;
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struct sun50i_a100_ledc_led leds[] __counted_by(num_leds);
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};
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static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, unsigned int length)
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{
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struct dma_async_tx_descriptor *desc;
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dma_cookie_t cookie;
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desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle,
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LEDS_TO_BYTES(length), DMA_MEM_TO_DEV, 0);
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if (!desc)
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return -ENOMEM;
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cookie = dmaengine_submit(desc);
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if (dma_submit_error(cookie))
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return -EIO;
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dma_async_issue_pending(priv->dma_chan);
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return 0;
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}
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static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, unsigned int fifo_used)
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{
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unsigned int burst, length, offset;
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u32 control;
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length = priv->pio_length;
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offset = priv->pio_offset;
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burst = min(length, LEDC_FIFO_DEPTH - fifo_used);
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iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst);
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if (burst < length) {
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priv->pio_length = length - burst;
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priv->pio_offset = offset + burst;
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if (!offset) {
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control = readl(priv->base + LEDC_INT_CTRL_REG);
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control |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
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writel(control, priv->base + LEDC_INT_CTRL_REG);
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}
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} else {
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/* Disable the request IRQ once all data is written. */
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control = readl(priv->base + LEDC_INT_CTRL_REG);
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control &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
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writel(control, priv->base + LEDC_INT_CTRL_REG);
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}
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}
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static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv, unsigned int length)
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{
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bool use_dma = false;
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u32 control;
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if (priv->dma_chan && length > LEDC_FIFO_DEPTH) {
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int ret;
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ret = sun50i_a100_ledc_dma_xfer(priv, length);
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if (ret)
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dev_warn(priv->dev, "Failed to set up DMA (%d), using PIO\n", ret);
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else
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use_dma = true;
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}
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/* The DMA trigger level must be at least the burst length. */
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control = FIELD_PREP(LEDC_DMA_CTRL_REG_DMA_EN, use_dma) |
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FIELD_PREP_CONST(LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL, LEDC_FIFO_DEPTH / 2);
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writel(control, priv->base + LEDC_DMA_CTRL_REG);
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control = readl(priv->base + LEDC_CTRL_REG);
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control &= ~LEDC_CTRL_REG_DATA_LENGTH;
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control |= FIELD_PREP(LEDC_CTRL_REG_DATA_LENGTH, length) | LEDC_CTRL_REG_LEDC_EN;
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writel(control, priv->base + LEDC_CTRL_REG);
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if (!use_dma) {
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/* The FIFO is empty when starting a new transfer. */
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unsigned int fifo_used = 0;
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priv->pio_length = length;
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priv->pio_offset = 0;
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sun50i_a100_ledc_pio_xfer(priv, fifo_used);
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}
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}
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static irqreturn_t sun50i_a100_ledc_irq(int irq, void *data)
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{
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struct sun50i_a100_ledc *priv = data;
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u32 status;
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status = readl(priv->base + LEDC_INT_STS_REG);
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if (status & LEDC_INT_STS_REG_TRANS_FINISH_INT) {
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unsigned int next_length;
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spin_lock(&priv->lock);
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/* If another transfer is queued, dequeue and start it. */
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next_length = priv->next_length;
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if (next_length)
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priv->next_length = 0;
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else
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priv->xfer_active = false;
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spin_unlock(&priv->lock);
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if (next_length)
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sun50i_a100_ledc_start_xfer(priv, next_length);
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} else if (status & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {
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/* Continue the current transfer. */
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sun50i_a100_ledc_pio_xfer(priv, FIELD_GET(LEDC_INT_STS_REG_FIFO_WLW, status));
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}
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/* Clear the W1C status bits. */
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writel(status, priv->base + LEDC_INT_STS_REG);
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return IRQ_HANDLED;
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}
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static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,
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enum led_brightness brightness)
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{
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struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent);
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struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
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struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);
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unsigned int next_length;
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unsigned long flags;
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bool xfer_active;
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led_mc_calc_color_components(mc_cdev, brightness);
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priv->buffer[led->addr] = led->subled_info[0].brightness << 16 |
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led->subled_info[1].brightness << 8 |
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led->subled_info[2].brightness;
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spin_lock_irqsave(&priv->lock, flags);
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/* Start, enqueue, or extend an enqueued transfer, as appropriate. */
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next_length = max(priv->next_length, led->addr + 1);
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xfer_active = priv->xfer_active;
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if (xfer_active)
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priv->next_length = next_length;
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else
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priv->xfer_active = true;
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spin_unlock_irqrestore(&priv->lock, flags);
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if (!xfer_active)
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sun50i_a100_ledc_start_xfer(priv, next_length);
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}
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static const char *const sun50i_a100_ledc_formats[] = {
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"rgb", "rbg", "grb", "gbr", "brg", "bgr",
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};
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static int sun50i_a100_ledc_parse_format(const struct device_node *np,
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struct sun50i_a100_ledc *priv)
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{
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const char *format = "grb";
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u32 i;
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of_property_read_string(np, "allwinner,pixel-format", &format);
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for (i = 0; i < ARRAY_SIZE(sun50i_a100_ledc_formats); i++) {
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if (!strcmp(format, sun50i_a100_ledc_formats[i])) {
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priv->format = i;
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return 0;
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}
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}
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return dev_err_probe(priv->dev, -EINVAL, "Bad pixel format '%s'\n", format);
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}
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static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)
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{
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u32 control;
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control = readl(priv->base + LEDC_CTRL_REG);
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control &= ~LEDC_CTRL_REG_RGB_MODE;
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control |= FIELD_PREP(LEDC_CTRL_REG_RGB_MODE, priv->format);
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writel(control, priv->base + LEDC_CTRL_REG);
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}
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static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {
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.t0h_ns = 336,
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.t0l_ns = 840,
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.t1h_ns = 882,
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.t1l_ns = 294,
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.treset_ns = 300000,
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};
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static int sun50i_a100_ledc_parse_timing(const struct device_node *np,
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struct sun50i_a100_ledc *priv)
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{
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struct sun50i_a100_ledc_timing *timing = &priv->timing;
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*timing = sun50i_a100_ledc_default_timing;
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of_property_read_u32(np, "allwinner,t0h-ns", &timing->t0h_ns);
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of_property_read_u32(np, "allwinner,t0l-ns", &timing->t0l_ns);
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of_property_read_u32(np, "allwinner,t1h-ns", &timing->t1h_ns);
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of_property_read_u32(np, "allwinner,t1l-ns", &timing->t1l_ns);
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of_property_read_u32(np, "allwinner,treset-ns", &timing->treset_ns);
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return 0;
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}
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static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)
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{
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const struct sun50i_a100_ledc_timing *timing = &priv->timing;
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unsigned long mod_freq = clk_get_rate(priv->mod_clk);
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u32 cycle_ns = NSEC_PER_SEC / mod_freq;
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u32 control;
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control = FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1H, timing->t1h_ns / cycle_ns) |
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FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T1L, timing->t1l_ns / cycle_ns) |
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FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0H, timing->t0h_ns / cycle_ns) |
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FIELD_PREP(LEDC_T01_TIMING_CTRL_REG_T0L, timing->t0l_ns / cycle_ns);
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writel(control, priv->base + LEDC_T01_TIMING_CTRL_REG);
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control = FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_TR, timing->treset_ns / cycle_ns) |
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FIELD_PREP(LEDC_RESET_TIMING_CTRL_REG_LED_NUM, priv->max_addr);
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writel(control, priv->base + LEDC_RESET_TIMING_CTRL_REG);
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}
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static int sun50i_a100_ledc_resume(struct device *dev)
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{
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struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
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int ret;
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ret = reset_control_deassert(priv->reset);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->bus_clk);
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if (ret)
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goto err_assert_reset;
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ret = clk_prepare_enable(priv->mod_clk);
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if (ret)
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goto err_disable_bus_clk;
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sun50i_a100_ledc_set_format(priv);
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sun50i_a100_ledc_set_timing(priv);
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writel(LEDC_INT_CTRL_REG_GLOBAL_INT_EN | LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN,
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priv->base + LEDC_INT_CTRL_REG);
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return 0;
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err_disable_bus_clk:
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clk_disable_unprepare(priv->bus_clk);
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err_assert_reset:
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reset_control_assert(priv->reset);
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return ret;
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}
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static int sun50i_a100_ledc_suspend(struct device *dev)
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{
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struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
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/* Wait for all transfers to complete. */
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for (;;) {
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unsigned long flags;
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bool xfer_active;
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spin_lock_irqsave(&priv->lock, flags);
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xfer_active = priv->xfer_active;
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spin_unlock_irqrestore(&priv->lock, flags);
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if (!xfer_active)
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break;
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msleep(1);
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}
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clk_disable_unprepare(priv->mod_clk);
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clk_disable_unprepare(priv->bus_clk);
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reset_control_assert(priv->reset);
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return 0;
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}
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static void sun50i_a100_ledc_dma_cleanup(void *data)
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{
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struct sun50i_a100_ledc *priv = data;
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dma_release_channel(priv->dma_chan);
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}
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static int sun50i_a100_ledc_probe(struct platform_device *pdev)
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{
|
||||
const struct device_node *np = pdev->dev.of_node;
|
||||
struct dma_slave_config dma_cfg = {};
|
||||
struct led_init_data init_data = {};
|
||||
struct sun50i_a100_ledc_led *led;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct sun50i_a100_ledc *priv;
|
||||
struct device_node *child;
|
||||
struct resource *mem;
|
||||
u32 max_addr = 0;
|
||||
u32 num_leds = 0;
|
||||
int irq, ret;
|
||||
|
||||
/*
|
||||
* The maximum LED address must be known in sun50i_a100_ledc_resume() before
|
||||
* class device registration, so parse and validate the subnodes up front.
|
||||
*/
|
||||
for_each_available_child_of_node(np, child) {
|
||||
u32 addr, color;
|
||||
|
||||
ret = of_property_read_u32(child, "reg", &addr);
|
||||
if (ret || addr >= LEDC_MAX_LEDS) {
|
||||
of_node_put(child);
|
||||
return dev_err_probe(dev, -EINVAL, "'reg' must be between 0 and %d\n",
|
||||
LEDC_MAX_LEDS - 1);
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(child, "color", &color);
|
||||
if (ret || color != LED_COLOR_ID_RGB) {
|
||||
of_node_put(child);
|
||||
return dev_err_probe(dev, -EINVAL, "'color' must be LED_COLOR_ID_RGB\n");
|
||||
}
|
||||
|
||||
max_addr = max(max_addr, addr);
|
||||
num_leds++;
|
||||
}
|
||||
|
||||
if (!num_leds)
|
||||
return -ENODEV;
|
||||
|
||||
priv = devm_kzalloc(dev, struct_size(priv, leds, num_leds), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->dev = dev;
|
||||
priv->max_addr = max_addr;
|
||||
priv->num_leds = num_leds;
|
||||
spin_lock_init(&priv->lock);
|
||||
dev_set_drvdata(dev, priv);
|
||||
|
||||
ret = sun50i_a100_ledc_parse_format(np, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sun50i_a100_ledc_parse_timing(np, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->bus_clk = devm_clk_get(dev, "bus");
|
||||
if (IS_ERR(priv->bus_clk))
|
||||
return PTR_ERR(priv->bus_clk);
|
||||
|
||||
priv->mod_clk = devm_clk_get(dev, "mod");
|
||||
if (IS_ERR(priv->mod_clk))
|
||||
return PTR_ERR(priv->mod_clk);
|
||||
|
||||
priv->reset = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (IS_ERR(priv->reset))
|
||||
return PTR_ERR(priv->reset);
|
||||
|
||||
priv->dma_chan = dma_request_chan(dev, "tx");
|
||||
if (IS_ERR(priv->dma_chan)) {
|
||||
if (PTR_ERR(priv->dma_chan) != -ENODEV)
|
||||
return PTR_ERR(priv->dma_chan);
|
||||
|
||||
priv->dma_chan = NULL;
|
||||
|
||||
priv->buffer = devm_kzalloc(dev, LEDS_TO_BYTES(LEDC_MAX_LEDS), GFP_KERNEL);
|
||||
if (!priv->buffer)
|
||||
return -ENOMEM;
|
||||
} else {
|
||||
ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
dma_cfg.dst_addr = mem->start + LEDC_DATA_REG;
|
||||
dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2;
|
||||
|
||||
ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->buffer = dmam_alloc_attrs(dmaengine_get_dma_device(priv->dma_chan),
|
||||
LEDS_TO_BYTES(LEDC_MAX_LEDS), &priv->dma_handle,
|
||||
GFP_KERNEL, DMA_ATTR_WRITE_COMBINE);
|
||||
if (!priv->buffer)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq, 0, dev_name(dev), priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sun50i_a100_ledc_resume(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
led = priv->leds;
|
||||
for_each_available_child_of_node(np, child) {
|
||||
struct led_classdev *cdev;
|
||||
|
||||
/* The node was already validated above. */
|
||||
of_property_read_u32(child, "reg", &led->addr);
|
||||
|
||||
led->subled_info[0].color_index = LED_COLOR_ID_RED;
|
||||
led->subled_info[0].channel = 0;
|
||||
led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
|
||||
led->subled_info[1].channel = 1;
|
||||
led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
|
||||
led->subled_info[2].channel = 2;
|
||||
|
||||
led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info);
|
||||
led->mc_cdev.subled_info = led->subled_info;
|
||||
|
||||
cdev = &led->mc_cdev.led_cdev;
|
||||
cdev->max_brightness = U8_MAX;
|
||||
cdev->brightness_set = sun50i_a100_ledc_brightness_set;
|
||||
|
||||
init_data.fwnode = of_fwnode_handle(child);
|
||||
|
||||
ret = led_classdev_multicolor_register_ext(dev, &led->mc_cdev, &init_data);
|
||||
if (ret) {
|
||||
dev_err_probe(dev, ret, "Failed to register multicolor LED %u", led->addr);
|
||||
goto err_put_child;
|
||||
}
|
||||
|
||||
led++;
|
||||
}
|
||||
|
||||
dev_info(dev, "Registered %u LEDs\n", num_leds);
|
||||
|
||||
return 0;
|
||||
|
||||
err_put_child:
|
||||
of_node_put(child);
|
||||
while (led-- > priv->leds)
|
||||
led_classdev_multicolor_unregister(&led->mc_cdev);
|
||||
sun50i_a100_ledc_suspend(&pdev->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sun50i_a100_ledc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sun50i_a100_ledc *priv = platform_get_drvdata(pdev);
|
||||
|
||||
for (u32 i = 0; i < priv->num_leds; i++)
|
||||
led_classdev_multicolor_unregister(&priv->leds[i].mc_cdev);
|
||||
sun50i_a100_ledc_suspend(&pdev->dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id sun50i_a100_ledc_of_match[] = {
|
||||
{ .compatible = "allwinner,sun50i-a100-ledc" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,
|
||||
sun50i_a100_ledc_suspend,
|
||||
sun50i_a100_ledc_resume);
|
||||
|
||||
static struct platform_driver sun50i_a100_ledc_driver = {
|
||||
.probe = sun50i_a100_ledc_probe,
|
||||
.remove_new = sun50i_a100_ledc_remove,
|
||||
.shutdown = sun50i_a100_ledc_remove,
|
||||
.driver = {
|
||||
.name = "sun50i-a100-ledc",
|
||||
.of_match_table = sun50i_a100_ledc_of_match,
|
||||
.pm = pm_ptr(&sun50i_a100_ledc_pm),
|
||||
},
|
||||
};
|
||||
module_platform_driver(sun50i_a100_ledc_driver);
|
||||
|
||||
MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
|
||||
MODULE_DESCRIPTION("Allwinner A100 LED controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user