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drm/radeon: add GET_PARAM/INFO support for Z pipes

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Needed for occlusion queries on rv530 chips.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2009-08-19 19:11:39 -04:00 committed by Dave Airlie
parent 17782d9950
commit f779b3e513
10 changed files with 39 additions and 4 deletions
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4
drivers/gpu/drm/radeon/r300.c
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@ -448,6 +448,7 @@ void r300_gpu_init(struct radeon_device *rdev)
/* rv350,rv370,rv380 */ /* rv350,rv370,rv380 */
rdev->num_gb_pipes = 1; rdev->num_gb_pipes = 1;
} }
rdev->num_z_pipes = 1;
gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch (rdev->num_gb_pipes) { switch (rdev->num_gb_pipes) {
case 2: case 2:
@ -486,7 +487,8 @@ void r300_gpu_init(struct radeon_device *rdev)
printk(KERN_WARNING "Failed to wait MC idle while " printk(KERN_WARNING "Failed to wait MC idle while "
"programming pipes. Bad things might happen.\n"); "programming pipes. Bad things might happen.\n");
} }
DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes); DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
rdev->num_gb_pipes, rdev->num_z_pipes);
} }
int r300_ga_reset(struct radeon_device *rdev) int r300_ga_reset(struct radeon_device *rdev)

13
drivers/gpu/drm/radeon/r420.c
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@ -165,7 +165,18 @@ void r420_pipes_init(struct radeon_device *rdev)
printk(KERN_WARNING "Failed to wait GUI idle while " printk(KERN_WARNING "Failed to wait GUI idle while "
"programming pipes. Bad things might happen.\n"); "programming pipes. Bad things might happen.\n");
} }
DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
if (rdev->family == CHIP_RV530) {
tmp = RREG32(RV530_GB_PIPE_SELECT2);
if ((tmp & 3) == 3)
rdev->num_z_pipes = 2;
else
rdev->num_z_pipes = 1;
} else
rdev->num_z_pipes = 1;
DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
rdev->num_gb_pipes, rdev->num_z_pipes);
} }
void r420_gpu_init(struct radeon_device *rdev) void r420_gpu_init(struct radeon_device *rdev)

1
drivers/gpu/drm/radeon/r520.c
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@ -177,7 +177,6 @@ void r520_gpu_init(struct radeon_device *rdev)
*/ */
/* workaround for RV530 */ /* workaround for RV530 */
if (rdev->family == CHIP_RV530) { if (rdev->family == CHIP_RV530) {
WREG32(0x4124, 1);
WREG32(0x4128, 0xFF); WREG32(0x4128, 0xFF);
} }
r420_pipes_init(rdev); r420_pipes_init(rdev);

1
drivers/gpu/drm/radeon/radeon.h
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@ -655,6 +655,7 @@ struct radeon_device {
int usec_timeout; int usec_timeout;
enum radeon_pll_errata pll_errata; enum radeon_pll_errata pll_errata;
int num_gb_pipes; int num_gb_pipes;
int num_z_pipes;
int disp_priority; int disp_priority;
/* BIOS */ /* BIOS */
uint8_t *bios; uint8_t *bios;

9
drivers/gpu/drm/radeon/radeon_cp.c
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@ -406,6 +406,15 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
{ {
uint32_t gb_tile_config, gb_pipe_sel = 0; uint32_t gb_tile_config, gb_pipe_sel = 0;
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
if ((z_pipe_sel & 3) == 3)
dev_priv->num_z_pipes = 2;
else
dev_priv->num_z_pipes = 1;
} else
dev_priv->num_z_pipes = 1;
/* RS4xx/RS6xx/R4xx/R5xx */ /* RS4xx/RS6xx/R4xx/R5xx */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);

5
drivers/gpu/drm/radeon/radeon_drv.h
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@ -100,9 +100,10 @@
* 1.28- Add support for VBL on CRTC2 * 1.28- Add support for VBL on CRTC2
* 1.29- R500 3D cmd buffer support * 1.29- R500 3D cmd buffer support
* 1.30- Add support for occlusion queries * 1.30- Add support for occlusion queries
* 1.31- Add support for num Z pipes from GET_PARAM
*/ */
#define DRIVER_MAJOR 1 #define DRIVER_MAJOR 1
#define DRIVER_MINOR 30 #define DRIVER_MINOR 31
#define DRIVER_PATCHLEVEL 0 #define DRIVER_PATCHLEVEL 0
/* /*
@ -329,6 +330,7 @@ typedef struct drm_radeon_private {
resource_size_t fb_aper_offset; resource_size_t fb_aper_offset;
int num_gb_pipes; int num_gb_pipes;
int num_z_pipes;
int track_flush; int track_flush;
drm_local_map_t *mmio; drm_local_map_t *mmio;
@ -689,6 +691,7 @@ extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pciga
/* pipe config regs */ /* pipe config regs */
#define R400_GB_PIPE_SELECT 0x402c #define R400_GB_PIPE_SELECT 0x402c
#define RV530_GB_PIPE_SELECT2 0x4124
#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
#define R300_GB_TILE_CONFIG 0x4018 #define R300_GB_TILE_CONFIG 0x4018
# define R300_ENABLE_TILING (1 << 0) # define R300_ENABLE_TILING (1 << 0)

3
drivers/gpu/drm/radeon/radeon_kms.c
View File

@ -95,6 +95,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case RADEON_INFO_NUM_GB_PIPES: case RADEON_INFO_NUM_GB_PIPES:
value = rdev->num_gb_pipes; value = rdev->num_gb_pipes;
break; break;
case RADEON_INFO_NUM_Z_PIPES:
value = rdev->num_z_pipes;
break;
default: default:
DRM_DEBUG("Invalid request %d\n", info->request); DRM_DEBUG("Invalid request %d\n", info->request);
return -EINVAL; return -EINVAL;

2
drivers/gpu/drm/radeon/radeon_reg.h
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@ -3574,4 +3574,6 @@
#define RADEON_SCRATCH_REG4 0x15f0 #define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4 #define RADEON_SCRATCH_REG5 0x15f4
#define RV530_GB_PIPE_SELECT2 0x4124
#endif #endif

3
drivers/gpu/drm/radeon/radeon_state.c
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@ -3081,6 +3081,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
case RADEON_PARAM_NUM_GB_PIPES: case RADEON_PARAM_NUM_GB_PIPES:
value = dev_priv->num_gb_pipes; value = dev_priv->num_gb_pipes;
break; break;
case RADEON_PARAM_NUM_Z_PIPES:
value = dev_priv->num_z_pipes;
break;
default: default:
DRM_DEBUG("Invalid parameter %d\n", param->param); DRM_DEBUG("Invalid parameter %d\n", param->param);
return -EINVAL; return -EINVAL;

2
include/drm/radeon_drm.h
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@ -709,6 +709,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ #define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
#define RADEON_PARAM_DEVICE_ID 16 #define RADEON_PARAM_DEVICE_ID 16
#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */
typedef struct drm_radeon_getparam { typedef struct drm_radeon_getparam {
int param; int param;
@ -897,6 +898,7 @@ struct drm_radeon_cs {
#define RADEON_INFO_DEVICE_ID 0x00 #define RADEON_INFO_DEVICE_ID 0x00
#define RADEON_INFO_NUM_GB_PIPES 0x01 #define RADEON_INFO_NUM_GB_PIPES 0x01
#define RADEON_INFO_NUM_Z_PIPES 0x02
struct drm_radeon_info { struct drm_radeon_info {
uint32_t request; uint32_t request;