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52e6676ef5
Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it
under the terms of the gnu general public license as published by the
free software foundation version 2 this program is distributed as is
without any warranty of any kind whether express or implied without
even the implied warranty of merchantability or fitness for a
particular purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
178 lines
5.2 KiB
C
178 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AM33XX Power domain data
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include "powerdomain.h"
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#include "prcm-common.h"
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#include "prm-regbits-33xx.h"
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#include "prm33xx.h"
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static struct powerdomain gfx_33xx_pwrdm = {
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.name = "gfx_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_GFX_MOD,
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.pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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.banks = 1,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
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.mem_on_mask = {
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[0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
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},
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.mem_ret_mask = {
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[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
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},
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.mem_pwrst_mask = {
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[0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
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},
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.mem_retst_mask = {
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[0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
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},
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* gfx_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* gfx_mem */
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},
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};
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static struct powerdomain rtc_33xx_pwrdm = {
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.name = "rtc_pwrdm",
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.voltdm = { .name = "rtc" },
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.prcm_offs = AM33XX_PRM_RTC_MOD,
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.pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_ON,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
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};
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static struct powerdomain wkup_33xx_pwrdm = {
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.name = "wkup_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_WKUP_MOD,
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.pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_ON,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
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};
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static struct powerdomain per_33xx_pwrdm = {
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.name = "per_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_PER_MOD,
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.pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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.banks = 3,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
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.mem_on_mask = {
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[0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
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[1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
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[2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
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},
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.mem_ret_mask = {
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[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
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[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
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[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
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},
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.mem_pwrst_mask = {
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[0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
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[1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
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[2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
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},
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.mem_retst_mask = {
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[0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
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[1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
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[2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
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},
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* pruss_mem */
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[1] = PWRSTS_OFF_RET, /* per_mem */
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[2] = PWRSTS_OFF_RET, /* ram_mem */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* pruss_mem */
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[1] = PWRSTS_ON, /* per_mem */
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[2] = PWRSTS_ON, /* ram_mem */
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},
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};
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static struct powerdomain mpu_33xx_pwrdm = {
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.name = "mpu_pwrdm",
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.voltdm = { .name = "mpu" },
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.prcm_offs = AM33XX_PRM_MPU_MOD,
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.pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_RET_ON,
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.pwrsts_logic_ret = PWRSTS_OFF_RET,
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
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.banks = 3,
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.logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
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.mem_on_mask = {
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[0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
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[1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
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[2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
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},
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.mem_ret_mask = {
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[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
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[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
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[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
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},
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.mem_pwrst_mask = {
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[0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
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[1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
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[2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
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},
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.mem_retst_mask = {
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[0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
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[1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
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[2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
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},
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.pwrsts_mem_ret = {
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[0] = PWRSTS_OFF_RET, /* mpu_l1 */
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[1] = PWRSTS_OFF_RET, /* mpu_l2 */
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[2] = PWRSTS_OFF_RET, /* mpu_ram */
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},
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.pwrsts_mem_on = {
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[0] = PWRSTS_ON, /* mpu_l1 */
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[1] = PWRSTS_ON, /* mpu_l2 */
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[2] = PWRSTS_ON, /* mpu_ram */
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},
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};
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static struct powerdomain cefuse_33xx_pwrdm = {
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.name = "cefuse_pwrdm",
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.voltdm = { .name = "core" },
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.prcm_offs = AM33XX_PRM_CEFUSE_MOD,
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.pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
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.pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
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.pwrsts = PWRSTS_OFF_ON,
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};
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static struct powerdomain *powerdomains_am33xx[] __initdata = {
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&gfx_33xx_pwrdm,
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&rtc_33xx_pwrdm,
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&wkup_33xx_pwrdm,
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&per_33xx_pwrdm,
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&mpu_33xx_pwrdm,
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&cefuse_33xx_pwrdm,
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NULL,
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};
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void __init am33xx_powerdomains_init(void)
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{
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pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
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pwrdm_register_pwrdms(powerdomains_am33xx);
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pwrdm_complete_init();
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}
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