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37e2d7d237
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. A couple of other includes are unused and can be dropped too. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright Altera Corporation (C) 2016. All rights reserved.
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "core.h"
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/* A10 System Manager L2 ECC Control register */
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#define A10_MPU_CTRL_L2_ECC_OFST 0x0
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#define A10_MPU_CTRL_L2_ECC_EN BIT(0)
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/* A10 System Manager Global IRQ Mask register */
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#define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
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#define A10_SYSMGR_ECC_INTMASK_CLR_L2 BIT(0)
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/* A10 System Manager L2 ECC IRQ Clear register */
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#define A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST 0xA8
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#define A10_SYSMGR_MPU_CLEAR_L2_ECC (BIT(31) | BIT(15))
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void socfpga_init_l2_ecc(void)
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{
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struct device_node *np;
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void __iomem *mapped_l2_edac_addr;
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
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if (!np) {
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pr_err("Unable to find socfpga-l2-ecc in dtb\n");
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return;
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}
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mapped_l2_edac_addr = of_iomap(np, 0);
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of_node_put(np);
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if (!mapped_l2_edac_addr) {
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pr_err("Unable to find L2 ECC mapping in dtb\n");
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return;
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}
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/* Enable ECC */
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writel(0x01, mapped_l2_edac_addr);
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iounmap(mapped_l2_edac_addr);
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}
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void socfpga_init_arria10_l2_ecc(void)
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{
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struct device_node *np;
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void __iomem *mapped_l2_edac_addr;
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/* Find the L2 EDAC device tree node */
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np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc");
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if (!np) {
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pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n");
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return;
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}
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mapped_l2_edac_addr = of_iomap(np, 0);
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of_node_put(np);
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if (!mapped_l2_edac_addr) {
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pr_err("Unable to find L2 ECC mapping in dtb\n");
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return;
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}
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if (!sys_manager_base_addr) {
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pr_err("System Manager not mapped for L2 ECC\n");
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goto exit;
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}
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/* Clear any pending IRQs */
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writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
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A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST));
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/* Enable ECC */
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writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
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A10_SYSMGR_ECC_INTMASK_CLR_OFST);
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writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
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A10_MPU_CTRL_L2_ECC_OFST);
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exit:
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iounmap(mapped_l2_edac_addr);
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}
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