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6d74d178fe
Many of the other architectures use their custom barrier implementations. Use the barrier code from the kernel sources to optimize barriers in tools. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Andrea Parri <parri.andrea@gmail.com> Link: https://lore.kernel.org/r/20240806-optimize_ring_buffer_read_riscv-v2-1-ca7e193ae198@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
14 lines
348 B
C
14 lines
348 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from the kernel sources to tools/arch/riscv:
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*/
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#ifndef _ASM_RISCV_FENCE_H
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#define _ASM_RISCV_FENCE_H
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#define RISCV_FENCE_ASM(p, s) "\tfence " #p "," #s "\n"
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#define RISCV_FENCE(p, s) \
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({ __asm__ __volatile__ (RISCV_FENCE_ASM(p, s) : : : "memory"); })
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#endif /* _ASM_RISCV_FENCE_H */
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