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https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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3abe84ea06
The description of second IO address is a bit confusing. It is supposed to be the MCC range which contains the slew rate registers, not the slew rate register base. The Linux driver then accesses slew rate register with hard-coded offset (0xa000). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
165 lines
4.3 KiB
YAML
165 lines
4.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM8450 SoC LPASS LPI TLMM
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maintainers:
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- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
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(LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
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properties:
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compatible:
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const: qcom,sm8450-lpass-lpi-pinctrl
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reg:
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items:
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- description: LPASS LPI TLMM Control and Status registers
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- description: LPASS LPI MCC registers
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clocks:
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items:
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- description: LPASS Core voting clock
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- description: LPASS Audio voting clock
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clock-names:
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items:
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- const: core
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- const: audio
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gpio-controller: true
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"#gpio-cells":
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description: Specifying the pin number and flags, as defined in
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include/dt-bindings/gpio/gpio.h
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const: 2
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gpio-ranges:
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maxItems: 1
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm8450-lpass-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm8450-lpass-state"
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additionalProperties: false
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$defs:
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qcom-sm8450-lpass-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: /schemas/pinctrl/pincfg-node.yaml
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
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function:
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enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
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dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk,
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dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data,
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qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws,
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i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk,
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wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data,
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slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data,
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ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d,
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ext_mclk1_e ]
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description:
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Specify the alternative function to be configured for the specified
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pins.
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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default: 2
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description:
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Selects the drive strength for the specified pins, in mA.
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slew-rate:
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enum: [0, 1, 2, 3]
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default: 0
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description: |
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0: No adjustments
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1: Higher Slew rate (faster edges)
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2: Lower Slew rate (slower edges)
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3: Reserved (No adjustments)
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bias-bus-hold: true
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bias-pull-down: true
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bias-pull-up: true
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bias-disable: true
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input-enable: true
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output-high: true
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output-low: true
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required:
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- pins
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- function
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additionalProperties: false
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- gpio-controller
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- "#gpio-cells"
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/sound/qcom,q6afe.h>
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pinctrl@3440000 {
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compatible = "qcom,sm8450-lpass-lpi-pinctrl";
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reg = <0x3440000 0x20000>,
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<0x34d0000 0x10000>;
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clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
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<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
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clock-names = "core", "audio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&lpi_tlmm 0 0 23>;
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wsa-swr-active-state {
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clk-pins {
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pins = "gpio10";
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function = "wsa_swr_clk";
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drive-strength = <2>;
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slew-rate = <1>;
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bias-disable;
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};
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data-pins {
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pins = "gpio11";
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function = "wsa_swr_data";
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drive-strength = <2>;
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slew-rate = <1>;
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};
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};
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tx-swr-sleep-clk-state {
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pins = "gpio0";
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function = "swr_tx_clk";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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