mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-18 06:15:12 +00:00
6cb1d2a158
Add 'output-enable' configuration parameter to the properties list.
Using these pinctrl properties observed hang issues with older Xilinx
ZynqMP Platform Management Firmware, hence reverted the patch previously.
Commit ff8356060e3a5e126abb ("Revert "dt-bindings: pinctrl-zynqmp: Add
output-enable configuration"").
Support for configuring these properties added in Xilinx ZynqMP Platform
Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware
driver checks if the configuration is supported by the PMUFW when it gets
request for TRISTATE configuration from pinctrl driver. If it supports,
then calls will be made otherwise it returns error.
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-4-sai.krishna.potthuri@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
343 lines
15 KiB
YAML
343 lines
15 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx ZynqMP Pinctrl
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maintainers:
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- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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description: |
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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ZynqMP's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, slew rate, etc.
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Each configuration node can consist of multiple nodes describing the pinmux and
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pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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properties:
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compatible:
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const: xlnx,zynqmp-pinctrl
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patternProperties:
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'^(.*-)?(default|gpio)$':
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type: object
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patternProperties:
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'^mux':
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type: object
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description:
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Pinctrl node's client devices use subnodes for pin muxes,
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which in turn use below standard properties.
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$ref: pinmux-node.yaml#
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properties:
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groups:
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description:
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List of groups to select (either this or "pins" must be
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specified), available groups for this subnode.
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items:
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enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp,
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ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp,
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gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp,
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mdio1_1_grp, mdio2_0_grp, mdio3_0_grp,
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qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp,
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spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp,
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spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp,
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spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp,
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spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp,
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spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp,
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spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp,
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spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp,
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spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp,
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spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp,
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spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp,
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spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp,
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spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp,
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spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp,
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spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp,
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spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp,
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spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp,
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sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
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sdio0_3_grp, sdio0_4_grp, sdio0_5_grp,
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sdio0_6_grp, sdio0_7_grp, sdio0_8_grp,
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sdio0_9_grp, sdio0_10_grp, sdio0_11_grp,
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sdio0_12_grp, sdio0_13_grp, sdio0_14_grp,
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sdio0_15_grp, sdio0_16_grp, sdio0_17_grp,
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sdio0_18_grp, sdio0_19_grp, sdio0_20_grp,
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sdio0_21_grp, sdio0_22_grp, sdio0_23_grp,
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sdio0_24_grp, sdio0_25_grp, sdio0_26_grp,
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sdio0_27_grp, sdio0_28_grp, sdio0_29_grp,
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sdio0_30_grp, sdio0_31_grp, sdio0_32_grp,
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sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp,
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sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp,
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sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp,
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sdio1_0_grp, sdio1_1_grp, sdio1_2_grp,
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sdio1_3_grp, sdio1_4_grp, sdio1_5_grp,
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sdio1_6_grp, sdio1_7_grp, sdio1_8_grp,
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sdio1_9_grp, sdio1_10_grp, sdio1_11_grp,
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sdio1_12_grp, sdio1_13_grp, sdio1_14_grp,
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sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp,
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sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp,
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sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp,
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nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp,
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nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp,
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can0_1_grp, can0_2_grp, can0_3_grp,
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can0_4_grp, can0_5_grp, can0_6_grp,
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can0_7_grp, can0_8_grp, can0_9_grp,
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can0_10_grp, can0_11_grp, can0_12_grp,
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can0_13_grp, can0_14_grp, can0_15_grp,
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can0_16_grp, can0_17_grp, can0_18_grp,
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can1_0_grp, can1_1_grp, can1_2_grp,
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can1_3_grp, can1_4_grp, can1_5_grp,
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can1_6_grp, can1_7_grp, can1_8_grp,
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can1_9_grp, can1_10_grp, can1_11_grp,
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can1_12_grp, can1_13_grp, can1_14_grp,
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can1_15_grp, can1_16_grp, can1_17_grp,
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can1_18_grp, can1_19_grp, uart0_0_grp,
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uart0_1_grp, uart0_2_grp, uart0_3_grp,
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uart0_4_grp, uart0_5_grp, uart0_6_grp,
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uart0_7_grp, uart0_8_grp, uart0_9_grp,
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uart0_10_grp, uart0_11_grp, uart0_12_grp,
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uart0_13_grp, uart0_14_grp, uart0_15_grp,
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uart0_16_grp, uart0_17_grp, uart0_18_grp,
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uart1_0_grp, uart1_1_grp, uart1_2_grp,
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uart1_3_grp, uart1_4_grp, uart1_5_grp,
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uart1_6_grp, uart1_7_grp, uart1_8_grp,
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uart1_9_grp, uart1_10_grp, uart1_11_grp,
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uart1_12_grp, uart1_13_grp, uart1_14_grp,
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uart1_15_grp, uart1_16_grp, uart1_17_grp,
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uart1_18_grp, i2c0_0_grp, i2c0_1_grp,
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i2c0_2_grp, i2c0_3_grp, i2c0_4_grp,
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i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
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i2c0_8_grp, i2c0_9_grp, i2c0_10_grp,
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i2c0_11_grp, i2c0_12_grp, i2c0_13_grp,
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i2c0_14_grp, i2c0_15_grp, i2c0_16_grp,
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i2c0_17_grp, i2c0_18_grp, i2c1_0_grp,
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i2c1_1_grp, i2c1_2_grp, i2c1_3_grp,
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i2c1_4_grp, i2c1_5_grp, i2c1_6_grp,
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i2c1_7_grp, i2c1_8_grp, i2c1_9_grp,
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i2c1_10_grp, i2c1_11_grp, i2c1_12_grp,
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i2c1_13_grp, i2c1_14_grp, i2c1_15_grp,
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i2c1_16_grp, i2c1_17_grp, i2c1_18_grp,
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i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp,
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ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp,
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ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp,
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ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp,
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ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp,
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ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp,
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ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp,
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ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp,
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ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp,
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ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp,
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ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp,
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ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp,
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ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp,
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ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp,
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ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp,
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ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp,
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ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp,
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ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp,
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ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp,
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ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp,
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ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp,
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ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp,
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ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp,
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ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp,
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ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp,
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swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp,
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swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp,
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swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp,
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swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp,
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swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp,
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swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp,
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swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp,
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swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp,
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swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp,
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swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp,
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swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp,
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swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp,
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swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp,
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swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp,
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swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp,
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swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp,
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swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp,
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gpio0_1_grp, gpio0_2_grp, gpio0_3_grp,
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gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
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gpio0_7_grp, gpio0_8_grp, gpio0_9_grp,
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gpio0_10_grp, gpio0_11_grp, gpio0_12_grp,
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gpio0_13_grp, gpio0_14_grp, gpio0_15_grp,
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gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
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gpio0_19_grp, gpio0_20_grp, gpio0_21_grp,
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gpio0_22_grp, gpio0_23_grp, gpio0_24_grp,
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gpio0_25_grp, gpio0_26_grp, gpio0_27_grp,
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gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
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gpio0_31_grp, gpio0_32_grp, gpio0_33_grp,
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gpio0_34_grp, gpio0_35_grp, gpio0_36_grp,
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gpio0_37_grp, gpio0_38_grp, gpio0_39_grp,
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gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
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gpio0_43_grp, gpio0_44_grp, gpio0_45_grp,
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gpio0_46_grp, gpio0_47_grp, gpio0_48_grp,
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gpio0_49_grp, gpio0_50_grp, gpio0_51_grp,
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gpio0_52_grp, gpio0_53_grp, gpio0_54_grp,
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gpio0_55_grp, gpio0_56_grp, gpio0_57_grp,
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gpio0_58_grp, gpio0_59_grp, gpio0_60_grp,
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gpio0_61_grp, gpio0_62_grp, gpio0_63_grp,
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gpio0_64_grp, gpio0_65_grp, gpio0_66_grp,
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gpio0_67_grp, gpio0_68_grp, gpio0_69_grp,
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gpio0_70_grp, gpio0_71_grp, gpio0_72_grp,
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gpio0_73_grp, gpio0_74_grp, gpio0_75_grp,
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gpio0_76_grp, gpio0_77_grp, usb0_0_grp,
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usb1_0_grp, pmu0_0_grp, pmu0_1_grp,
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pmu0_2_grp, pmu0_3_grp, pmu0_4_grp,
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pmu0_5_grp, pmu0_6_grp, pmu0_7_grp,
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pmu0_8_grp, pmu0_9_grp, pmu0_10_grp,
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pmu0_11_grp, pcie0_0_grp, pcie0_1_grp,
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pcie0_2_grp, pcie0_3_grp, pcie0_4_grp,
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pcie0_5_grp, pcie0_6_grp, pcie0_7_grp,
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csu0_0_grp, csu0_1_grp, csu0_2_grp,
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csu0_3_grp, csu0_4_grp, csu0_5_grp,
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csu0_6_grp, csu0_7_grp, csu0_8_grp,
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csu0_9_grp, csu0_10_grp, csu0_11_grp,
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dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp,
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dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp,
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pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp,
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pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp,
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trace0_1_grp, trace0_clk_1_grp, trace0_2_grp,
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trace0_clk_2_grp, testscan0_0_grp]
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maxItems: 78
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function:
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description:
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Specify the alternative function to be configured for the
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given pin groups.
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enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0,
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mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss,
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spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp,
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sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
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i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav,
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ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0,
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pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0]
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required:
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- groups
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- function
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additionalProperties: false
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'^conf':
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type: object
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description:
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Pinctrl node's client devices use subnodes for pin configurations,
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which in turn use the standard properties below.
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$ref: pincfg-node.yaml#
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properties:
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groups:
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description:
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List of pin groups as mentioned above.
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pins:
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description:
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List of pin names to select in this subnode.
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items:
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pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$'
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maxItems: 78
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bias-pull-up: true
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bias-pull-down: true
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bias-disable: true
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input-schmitt-enable: true
|
|
|
|
input-schmitt-disable: true
|
|
|
|
bias-high-impedance: true
|
|
|
|
low-power-enable: true
|
|
|
|
low-power-disable: true
|
|
|
|
slew-rate:
|
|
enum: [0, 1]
|
|
|
|
output-enable:
|
|
description:
|
|
This will internally disable the tri-state for MIO pins.
|
|
|
|
drive-strength:
|
|
description:
|
|
Selects the drive strength for MIO pins, in mA.
|
|
enum: [2, 4, 8, 12]
|
|
|
|
power-source:
|
|
enum: [0, 1]
|
|
|
|
oneOf:
|
|
- required: [ groups ]
|
|
- required: [ pins ]
|
|
|
|
additionalProperties: false
|
|
|
|
additionalProperties: false
|
|
|
|
allOf:
|
|
- $ref: pinctrl.yaml#
|
|
|
|
required:
|
|
- compatible
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
|
zynqmp_firmware: zynqmp-firmware {
|
|
pinctrl0: pinctrl {
|
|
compatible = "xlnx,zynqmp-pinctrl";
|
|
|
|
pinctrl_uart1_default: uart1-default {
|
|
mux {
|
|
groups = "uart0_4_grp", "uart0_5_grp";
|
|
function = "uart0";
|
|
};
|
|
|
|
conf {
|
|
groups = "uart0_4_grp";
|
|
slew-rate = <SLEW_RATE_SLOW>;
|
|
power-source = <IO_STANDARD_LVCMOS18>;
|
|
};
|
|
|
|
conf-rx {
|
|
pins = "MIO18";
|
|
bias-pull-up;
|
|
};
|
|
|
|
conf-tx {
|
|
pins = "MIO19";
|
|
bias-disable;
|
|
input-schmitt-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1_default>;
|
|
};
|
|
|
|
...
|