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0ed1325967
Architectures for which we have hardware walkers of Linux page table
should flush TLB on mmu gather batch allocation failures and batch flush.
Some architectures like POWER supports multiple translation modes (hash
and radix) and in the case of POWER only radix translation mode needs the
above TLBI. This is because for hash translation mode kernel wants to
avoid this extra flush since there are no hardware walkers of linux page
table. With radix translation, the hardware also walks linux page table
and with that, kernel needs to make sure to TLB invalidate page walk cache
before page table pages are freed.
More details in commit d86564a2f085 ("mm/tlb, x86/mm: Support invalidating
TLB caches for RCU_TABLE_FREE")
The changes to sparc are to make sure we keep the old behavior since we
are now removing HAVE_RCU_TABLE_NO_INVALIDATE. The default value for
tlb_needs_table_invalidate is to always force an invalidate and sparc can
avoid the table invalidate. Hence we define tlb_needs_table_invalidate to
false for sparc architecture.
Link: http://lkml.kernel.org/r/20200116064531.483522-3-aneesh.kumar@linux.ibm.com
Fixes: a46cc7a90fd8 ("powerpc/mm/radix: Improve TLB/PWC flushes")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Acked-by: Michael Ellerman <mpe@ellerman.id.au> [powerpc]
Cc: <stable@vger.kernel.org> [4.14+]
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* TLB shootdown specifics for powerpc
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*
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* Copyright (C) 2002 Anton Blanchard, IBM Corp.
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* Copyright (C) 2002 Paul Mackerras, IBM Corp.
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*/
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#ifndef _ASM_POWERPC_TLB_H
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#define _ASM_POWERPC_TLB_H
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#ifdef __KERNEL__
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#ifndef __powerpc64__
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#include <asm/pgtable.h>
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#endif
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#include <asm/pgalloc.h>
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#ifndef __powerpc64__
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#include <asm/page.h>
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#include <asm/mmu.h>
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#endif
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#include <linux/pagemap.h>
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry __tlb_remove_tlb_entry
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#define tlb_flush tlb_flush
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extern void tlb_flush(struct mmu_gather *tlb);
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/*
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* book3s:
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* Hash does not use the linux page-tables, so we can avoid
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* the TLB invalidate for page-table freeing, Radix otoh does use the
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* page-tables and needs the TLBI.
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*
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* nohash:
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* We still do TLB invalidate in the __pte_free_tlb routine before we
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* add the page table pages to mmu gather table batch.
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*/
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#define tlb_needs_table_invalidate() radix_enabled()
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/* Get the generic bits... */
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#include <asm-generic/tlb.h>
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extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
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unsigned long address);
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static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
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unsigned long address)
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{
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#ifdef CONFIG_PPC_BOOK3S_32
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(tlb->mm, ptep, address);
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#endif
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}
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#ifdef CONFIG_SMP
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static inline int mm_is_core_local(struct mm_struct *mm)
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{
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return cpumask_subset(mm_cpumask(mm),
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topology_sibling_cpumask(smp_processor_id()));
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}
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#ifdef CONFIG_PPC_BOOK3S_64
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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if (atomic_read(&mm->context.active_cpus) > 1)
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return false;
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return cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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static inline void mm_reset_thread_local(struct mm_struct *mm)
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{
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WARN_ON(atomic_read(&mm->context.copros) > 0);
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/*
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* It's possible for mm_access to take a reference on mm_users to
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* access the remote mm from another thread, but it's not allowed
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* to set mm_cpumask, so mm_users may be > 1 here.
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*/
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WARN_ON(current->mm != mm);
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atomic_set(&mm->context.active_cpus, 1);
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cpumask_clear(mm_cpumask(mm));
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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#else /* CONFIG_PPC_BOOK3S_64 */
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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return cpumask_equal(mm_cpumask(mm),
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cpumask_of(smp_processor_id()));
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}
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#endif /* !CONFIG_PPC_BOOK3S_64 */
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#else /* CONFIG_SMP */
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static inline int mm_is_core_local(struct mm_struct *mm)
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{
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return 1;
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}
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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return 1;
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}
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_TLB_H */
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