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ace5029856
Merge updates of the powercap framework, generic PM domains, Energy Model and operating performance points for 6.3-rc1: - Fix possible name leak in powercap_register_zone() (Yang Yingliang). - Add Meteor Lake and Emerald Rapids support to the intel_rapl power capping driver (Zhang Rui). - Modify the idle_inject power capping facility to support 100% idle injection (Srinivas Pandruvada). - Fix large time windows handling in the intel_rapl power capping driver (Zhang Rui). - Fix memory leaks with using debugfs_lookup() in the generic PM domains and Energy Model code (Greg Kroah-Hartman). - Add missing 'cache-unified' property in example for kryo OPP bindings (Rob Herring). - Fix error checking in opp_migrate_dentry() (Qi Zheng). - Remove "select SRCU" (Paul E. McKenney). - Let qcom,opp-fuse-level be a 2-long array for qcom SoCs (Konrad Dybcio). * powercap: powercap: intel_rapl: Fix handling for large time window powercap: idle_inject: Support 100% idle injection powercap: intel_rapl: add support for Emerald Rapids powercap: intel_rapl: add support for Meteor Lake powercap: fix possible name leak in powercap_register_zone() * pm-domains: PM: domains: fix memory leak with using debugfs_lookup() * pm-em: PM: EM: fix memory leak with using debugfs_lookup() * pm-opp: OPP: fix error checking in opp_migrate_dentry() dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array drivers/opp: Remove "select SRCU" dt-bindings: opp: opp-v2-kryo-cpu: Add missing 'cache-unified' property in example
282 lines
8.4 KiB
YAML
282 lines
8.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. NVMEM OPP
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maintainers:
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- Ilia Lin <ilia.lin@kernel.org>
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allOf:
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- $ref: opp-v2-base.yaml#
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description: |
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In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
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the CPU frequencies subset and voltage value of each OPP varies based on
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the silicon variant in use.
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Qualcomm Technologies, Inc. Process Voltage Scaling Tables
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defines the voltage and frequency value based on the speedbin blown in
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the efuse combination.
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The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide
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the OPP framework with required information (existing HW bitmap).
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This is used to determine the voltage and frequency value for each OPP of
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operating-points-v2 table when it is parsed by the OPP framework.
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properties:
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compatible:
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const: operating-points-v2-kryo-cpu
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nvmem-cells:
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description: |
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A phandle pointing to a nvmem-cells node representing the
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efuse registers that has information about the
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speedbin that is used to select the right frequency/voltage
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value pair.
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opp-shared: true
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patternProperties:
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'^opp-?[0-9]+$':
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type: object
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additionalProperties: false
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properties:
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opp-hz: true
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opp-microvolt: true
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opp-supported-hw:
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description: |
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A single 32 bit bitmap value, representing compatible HW.
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Bitmap for MSM8996 format:
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0: MSM8996, speedbin 0
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1: MSM8996, speedbin 1
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2: MSM8996, speedbin 2
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3: MSM8996, speedbin 3
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4-31: unused
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Bitmap for MSM8996SG format (speedbin shifted of 4 left):
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0-3: unused
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4: MSM8996SG, speedbin 0
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5: MSM8996SG, speedbin 1
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6: MSM8996SG, speedbin 2
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7-31: unused
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enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
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0x9, 0xd, 0xe, 0xf,
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0x10, 0x20, 0x30, 0x70]
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clock-latency-ns: true
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required-opps: true
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required:
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- opp-hz
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required:
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- compatible
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if:
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required:
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- nvmem-cells
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then:
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patternProperties:
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'^opp-?[0-9]+$':
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required:
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- opp-supported-hw
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additionalProperties: false
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examples:
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- |
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/ {
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model = "Qualcomm Technologies, Inc. DB820c";
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compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 0>;
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operating-points-v2 = <&cluster0_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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clocks = <&kryocc 1>;
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operating-points-v2 = <&cluster1_opp>;
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power-domains = <&cpr>;
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power-domain-names = "cpr";
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#cooling-cells = <2>;
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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cluster0_opp: opp-table-0 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp1>;
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};
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opp-1401600000 {
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opp-hz = /bits/ 64 <1401600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x5>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp2>;
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};
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opp-1593600000 {
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opp-hz = /bits/ 64 <1593600000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp3>;
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};
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};
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cluster1_opp: opp-table-1 {
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compatible = "operating-points-v2-kryo-cpu";
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nvmem-cells = <&speedbin_efuse>;
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opp-shared;
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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opp-microvolt = <905000 905000 1140000>;
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opp-supported-hw = <0x7>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp1>;
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};
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opp-1804800000 {
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opp-hz = /bits/ 64 <1804800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x6>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp4>;
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};
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opp-1900800000 {
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opp-hz = /bits/ 64 <1900800000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x4>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp5>;
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};
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opp-2150400000 {
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opp-hz = /bits/ 64 <2150400000>;
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opp-microvolt = <1140000 905000 1140000>;
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opp-supported-hw = <0x1>;
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clock-latency-ns = <200000>;
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required-opps = <&cpr_opp6>;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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qfprom: qfprom@74000 {
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compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
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reg = <0x00074000 0x8ff>;
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#address-cells = <1>;
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#size-cells = <1>;
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speedbin_efuse: speedbin@133 {
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reg = <0x133 0x1>;
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bits = <5 3>;
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};
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};
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};
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};
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