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3c30cc26df
We create a custom compatible for the STA2X11 IP block as integrated into the Mobileye EyeQ5 platform. Its wake and alternate functions have been disabled, we want to avoid touching those registers. We both do: (1) early return in functions that do not support the platform, but with warnings, and (2) avoid calling those functions in the first place. We ensure that pinctrl-nomadik is not used with this STA2X11 variant. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20240228-mbly-gpio-v2-24-3ba757474006@bootlin.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
278 lines
7.2 KiB
C
278 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_GPIO_NOMADIK_H
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#define __LINUX_GPIO_NOMADIK_H
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/* Package definitions */
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#define PINCTRL_NMK_STN8815 0
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#define PINCTRL_NMK_DB8500 1
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#define GPIO_BLOCK_SHIFT 5
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#define NMK_GPIO_PER_CHIP BIT(GPIO_BLOCK_SHIFT)
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#define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
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/* Register in the logic block */
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#define NMK_GPIO_DAT 0x00
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#define NMK_GPIO_DATS 0x04
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#define NMK_GPIO_DATC 0x08
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#define NMK_GPIO_PDIS 0x0c
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#define NMK_GPIO_DIR 0x10
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#define NMK_GPIO_DIRS 0x14
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#define NMK_GPIO_DIRC 0x18
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#define NMK_GPIO_SLPC 0x1c
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#define NMK_GPIO_AFSLA 0x20
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#define NMK_GPIO_AFSLB 0x24
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#define NMK_GPIO_LOWEMI 0x28
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#define NMK_GPIO_RIMSC 0x40
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#define NMK_GPIO_FIMSC 0x44
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#define NMK_GPIO_IS 0x48
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#define NMK_GPIO_IC 0x4c
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#define NMK_GPIO_RWIMSC 0x50
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#define NMK_GPIO_FWIMSC 0x54
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#define NMK_GPIO_WKS 0x58
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/* These appear in DB8540 and later ASICs */
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#define NMK_GPIO_EDGELEVEL 0x5C
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#define NMK_GPIO_LEVEL 0x60
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/* Pull up/down values */
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enum nmk_gpio_pull {
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NMK_GPIO_PULL_NONE,
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NMK_GPIO_PULL_UP,
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NMK_GPIO_PULL_DOWN,
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};
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/* Sleep mode */
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enum nmk_gpio_slpm {
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NMK_GPIO_SLPM_INPUT,
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NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
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NMK_GPIO_SLPM_NOCHANGE,
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NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
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};
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struct nmk_gpio_chip {
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struct gpio_chip chip;
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void __iomem *addr;
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struct clk *clk;
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unsigned int bank;
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void (*set_ioforce)(bool enable);
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spinlock_t lock;
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bool sleepmode;
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bool is_mobileye_soc;
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/* Keep track of configured edges */
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u32 edge_rising;
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u32 edge_falling;
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u32 real_wake;
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u32 rwimsc;
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u32 fwimsc;
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u32 rimsc;
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u32 fimsc;
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u32 pull_up;
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u32 lowemi;
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};
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/* Alternate functions: function C is set in hw by setting both A and B */
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#define NMK_GPIO_ALT_GPIO 0
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#define NMK_GPIO_ALT_A 1
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#define NMK_GPIO_ALT_B 2
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#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
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#define NMK_GPIO_ALT_CX_SHIFT 2
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#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
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#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
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#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
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#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
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#define PRCM_GPIOCR_ALTCX(pin_num,\
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altc1_used, altc1_ri, altc1_cb,\
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altc2_used, altc2_ri, altc2_cb,\
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altc3_used, altc3_ri, altc3_cb,\
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altc4_used, altc4_ri, altc4_cb)\
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{\
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.pin = pin_num,\
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.altcx[PRCM_IDX_GPIOCR_ALTC1] = {\
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.used = altc1_used,\
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.reg_index = altc1_ri,\
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.control_bit = altc1_cb\
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},\
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.altcx[PRCM_IDX_GPIOCR_ALTC2] = {\
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.used = altc2_used,\
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.reg_index = altc2_ri,\
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.control_bit = altc2_cb\
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},\
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.altcx[PRCM_IDX_GPIOCR_ALTC3] = {\
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.used = altc3_used,\
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.reg_index = altc3_ri,\
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.control_bit = altc3_cb\
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},\
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.altcx[PRCM_IDX_GPIOCR_ALTC4] = {\
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.used = altc4_used,\
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.reg_index = altc4_ri,\
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.control_bit = altc4_cb\
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},\
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}
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/**
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* enum prcm_gpiocr_reg_index
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* Used to reference an PRCM GPIOCR register address.
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*/
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enum prcm_gpiocr_reg_index {
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PRCM_IDX_GPIOCR1,
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PRCM_IDX_GPIOCR2,
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PRCM_IDX_GPIOCR3
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};
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/**
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* enum prcm_gpiocr_altcx_index
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* Used to reference an Other alternate-C function.
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*/
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enum prcm_gpiocr_altcx_index {
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PRCM_IDX_GPIOCR_ALTC1,
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PRCM_IDX_GPIOCR_ALTC2,
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PRCM_IDX_GPIOCR_ALTC3,
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PRCM_IDX_GPIOCR_ALTC4,
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PRCM_IDX_GPIOCR_ALTC_MAX,
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};
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/**
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* struct prcm_gpio_altcx - Other alternate-C function
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* @used: other alternate-C function availability
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* @reg_index: PRCM GPIOCR register index used to control the function
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* @control_bit: PRCM GPIOCR bit used to control the function
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*/
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struct prcm_gpiocr_altcx {
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bool used:1;
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u8 reg_index:2;
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u8 control_bit:5;
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} __packed;
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/**
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* struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
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* @pin: The pin number
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* @altcx: array of other alternate-C[1-4] functions
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*/
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struct prcm_gpiocr_altcx_pin_desc {
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unsigned short pin;
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struct prcm_gpiocr_altcx altcx[PRCM_IDX_GPIOCR_ALTC_MAX];
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};
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/**
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* struct nmk_function - Nomadik pinctrl mux function
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* @name: The name of the function, exported to pinctrl core.
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* @groups: An array of pin groups that may select this function.
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* @ngroups: The number of entries in @groups.
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*/
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struct nmk_function {
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const char *name;
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const char * const *groups;
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unsigned int ngroups;
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};
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/**
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* struct nmk_pingroup - describes a Nomadik pin group
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* @grp: Generic data of the pin group (name and pins)
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* @altsetting: the altsetting to apply to all pins in this group to
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* configure them to be used by a function
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*/
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struct nmk_pingroup {
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struct pingroup grp;
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int altsetting;
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};
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#define NMK_PIN_GROUP(a, b) \
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{ \
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.grp = PINCTRL_PINGROUP(#a, a##_pins, ARRAY_SIZE(a##_pins)), \
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.altsetting = b, \
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}
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/**
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* struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
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* @pins: An array describing all pins the pin controller affects.
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* All pins which are also GPIOs must be listed first within the
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* array, and be numbered identically to the GPIO controller's
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* numbering.
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* @npins: The number of entries in @pins.
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* @functions: The functions supported on this SoC.
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* @nfunction: The number of entries in @functions.
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* @groups: An array describing all pin groups the pin SoC supports.
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* @ngroups: The number of entries in @groups.
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* @altcx_pins: The pins that support Other alternate-C function on this SoC
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* @npins_altcx: The number of Other alternate-C pins
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* @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC
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*/
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struct nmk_pinctrl_soc_data {
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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const struct nmk_function *functions;
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unsigned int nfunctions;
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const struct nmk_pingroup *groups;
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unsigned int ngroups;
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const struct prcm_gpiocr_altcx_pin_desc *altcx_pins;
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unsigned int npins_altcx;
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const u16 *prcm_gpiocr_registers;
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};
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#ifdef CONFIG_PINCTRL_STN8815
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void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
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#else
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static inline void
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nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
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{
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}
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#endif
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#ifdef CONFIG_PINCTRL_DB8500
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void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
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#else
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static inline void
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nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
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{
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}
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#endif
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#ifdef CONFIG_PINCTRL_DB8540
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void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
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#else
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static inline void
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nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
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{
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}
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#endif
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struct platform_device;
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/*
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* Symbols declared in gpio-nomadik used by pinctrl-nomadik. If pinctrl-nomadik
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* is enabled, then gpio-nomadik is enabled as well; the reverse if not always
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* true.
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*/
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void nmk_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev,
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struct gpio_chip *chip, unsigned int offset,
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unsigned int gpio);
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void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
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unsigned int offset, int val);
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void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, unsigned int offset,
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enum nmk_gpio_slpm mode);
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struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
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struct platform_device *pdev);
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/* Symbols declared in pinctrl-nomadik used by gpio-nomadik. */
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#ifdef CONFIG_PINCTRL_NOMADIK
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extern struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
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extern spinlock_t nmk_gpio_slpm_lock;
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int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev,
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int gpio);
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#endif
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#endif /* __LINUX_GPIO_NOMADIK_H */
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