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History

Arnd Bergmann 482069ebdc

riscv: dma-mapping: skip invalidation before bidirectional DMA

For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned
first to let the device see data written by the CPU, and invalidated
after the transfer to let the CPU see data written by the device.

riscv also invalidates the caches before the transfer, which does
not appear to serve any purpose.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20230816232336.164413-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2023-09-01 09:07:45 -07:00

boot

RISC-V Devicetrees for v6.5 Part 2

2023-06-20 23:06:54 +02:00

configs

RISC-V Patches for the 6.5 Merge Window, Part 1

2023-06-30 09:37:26 -07:00

errata

Merge patch series "riscv: some CMO alternative related clean up"

2023-07-06 10:32:38 -07:00

include

RISC-V Patches for the 6.5 Merge Window, Part 2