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4946d58dbb
The cells for the Crystal Cove PMIC are already mostly sorted by function / IRQ order. Move the ADC cell so that they are fully sorted. Also move some of the resource definitions so that their order matches the (new) order of the cells. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20211225115509.94891-2-hdegoede@redhat.com
141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device access for Crystal Cove PMIC
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*
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* Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include "intel_soc_pmic_core.h"
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#define CRYSTAL_COVE_MAX_REGISTER 0xC6
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#define CRYSTAL_COVE_REG_IRQLVL1 0x02
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#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
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#define CRYSTAL_COVE_IRQ_PWRSRC 0
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#define CRYSTAL_COVE_IRQ_THRM 1
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#define CRYSTAL_COVE_IRQ_BCU 2
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#define CRYSTAL_COVE_IRQ_ADC 3
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#define CRYSTAL_COVE_IRQ_CHGR 4
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#define CRYSTAL_COVE_IRQ_GPIO 5
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#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
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static const struct resource pwrsrc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
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};
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static const struct resource thermal_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
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};
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static const struct resource bcu_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
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};
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static const struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
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};
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static const struct resource gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
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};
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static struct mfd_cell crystal_cove_byt_dev[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_adc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "byt_crystal_cove_pmic",
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static struct mfd_cell crystal_cove_cht_dev[] = {
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "cht_crystal_cove_pmic",
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static const struct regmap_config crystal_cove_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = CRYSTAL_COVE_MAX_REGISTER,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
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};
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static const struct regmap_irq_chip crystal_cove_irq_chip = {
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.name = "Crystal Cove",
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.irqs = crystal_cove_irqs,
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.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
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.num_regs = 1,
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.status_base = CRYSTAL_COVE_REG_IRQLVL1,
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.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_byt_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_cht_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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