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cf3e10cc0e
dtc generates the following warning when building the LAN966x devicetree
overlay (lan966x_pci.dtso):
Warning (interrupts_property): /fragment@0/__overlay__/pci-ep-bus@0/oic@e00c0120: Missing interrupt-parent
The oic interrupt parent is the PCI device itself. The PCI device node
is the node on which the dtbo will be applied and this node already has
properties needed.
In order to remove the warning, add the missing properties in the
overlay fragment node. Properties in this node will not be added when
the overlay is applied (which is what we expect) but makes dtc happy.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Closes: https://lore.kernel.org/all/20241025110919.64b1cffb@canb.auug.org.au/
Fixes: 185686beb4 ("misc: Add support for LAN966x PCI device")
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241029084338.194942-3-herve.codina@bootlin.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
178 lines
4.0 KiB
Plaintext
178 lines
4.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Microchip UNG
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*/
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#include <dt-bindings/clock/microchip,lan966x.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/mfd/atmel-flexcom.h>
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#include <dt-bindings/phy/phy-lan966x-serdes.h>
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/dts-v1/;
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/plugin/;
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/ {
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fragment@0 {
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target-path = "";
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/*
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* These properties allow to avoid a dtc warnings.
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* The real interrupt controller is the PCI device itself. It
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* is the node on which the device tree overlay will be applied.
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* This node has those properties.
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*/
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#interrupt-cells = <1>;
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interrupt-controller;
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__overlay__ {
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#address-cells = <3>;
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#size-cells = <2>;
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cpu_clk: clock-600000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>; /* CPU clock = 600MHz */
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};
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ddr_clk: clock-30000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>; /* Fabric clock = 30MHz */
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};
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sys_clk: clock-15625000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <15625000>; /* System clock = 15.625MHz */
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};
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pci-ep-bus@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* map @0xe2000000 (32MB) to BAR0 (CPU)
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* map @0xe0000000 (16MB) to BAR1 (AMBA)
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*/
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ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
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0xe0000000 0x01 0x00 0x00 0x1000000>;
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oic: oic@e00c0120 {
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compatible = "microchip,lan966x-oic";
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts = <0>; /* PCI INTx assigned interrupt */
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reg = <0xe00c0120 0x190>;
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};
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cpu_ctrl: syscon@e00c0000 {
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compatible = "microchip,lan966x-cpu-syscon", "syscon";
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reg = <0xe00c0000 0xa8>;
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};
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reset: reset@e200400c {
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compatible = "microchip,lan966x-switch-reset";
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reg = <0xe200400c 0x4>, <0xe00c0000 0xa8>;
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reg-names = "gcb","cpu";
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#reset-cells = <1>;
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cpu-syscon = <&cpu_ctrl>;
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};
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gpio: pinctrl@e2004064 {
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compatible = "microchip,lan966x-pinctrl";
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reg = <0xe2004064 0xb4>,
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<0xe2010024 0x138>;
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resets = <&reset 0>;
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reset-names = "switch";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&gpio 0 0 78>;
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interrupt-parent = <&oic>;
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interrupt-controller;
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interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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tod_pins: tod_pins {
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pins = "GPIO_36";
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function = "ptpsync_1";
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};
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fc0_a_pins: fcb4-i2c-pins {
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/* RXD, TXD */
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pins = "GPIO_9", "GPIO_10";
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function = "fc0_a";
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};
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};
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serdes: serdes@e202c000 {
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compatible = "microchip,lan966x-serdes";
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reg = <0xe202c000 0x9c>,
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<0xe2004010 0x4>;
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#phy-cells = <2>;
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};
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mdio1: mdio@e200413c {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "microchip,lan966x-miim";
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reg = <0xe200413c 0x24>,
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<0xe2010020 0x4>;
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resets = <&reset 0>;
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reset-names = "switch";
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lan966x_phy0: ethernet-lan966x_phy@1 {
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reg = <1>;
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};
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lan966x_phy1: ethernet-lan966x_phy@2 {
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reg = <2>;
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};
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};
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switch: switch@e0000000 {
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compatible = "microchip,lan966x-switch";
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reg = <0xe0000000 0x0100000>,
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<0xe2000000 0x0800000>;
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reg-names = "cpu", "gcb";
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interrupt-parent = <&oic>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
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<9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "xtr", "ana";
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resets = <&reset 0>;
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reset-names = "switch";
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pinctrl-names = "default";
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pinctrl-0 = <&tod_pins>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0: port@0 {
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phy-handle = <&lan966x_phy0>;
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reg = <0>;
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phy-mode = "gmii";
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phys = <&serdes 0 CU(0)>;
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};
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port1: port@1 {
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phy-handle = <&lan966x_phy1>;
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reg = <1>;
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phy-mode = "gmii";
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phys = <&serdes 1 CU(1)>;
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};
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};
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};
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};
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};
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};
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};
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