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9fb1e654dc
When high-speed DMA paths are used to transfer arbitrary data over a Thunderbolt link, DMA rings should be in frame mode instead of raw mode. The latter is used by the control channel (ring 0). In frame mode each data frame can hold up to 4kB payload. This patch modifies the DMA ring code to allow configuring a ring to be in frame mode by passing a new flag (RING_FLAG_FRAME) to the ring when it is allocated. In addition there might be need to enable end-to-end (E2E) workaround for the ring to prevent losing Rx frames in certain situations. We add another flag (RING_FLAG_E2E) that can be used for this purpose. This code is based on the work done by Amir Levy and Michael Jamet. Signed-off-by: Michael Jamet <michael.jamet@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Yehezkel Bernat <yehezkel.bernat@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/*
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* Thunderbolt driver - NHI registers
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*
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* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
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*/
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#ifndef NHI_REGS_H_
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#define NHI_REGS_H_
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#include <linux/types.h>
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enum ring_flags {
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RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
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RING_FLAG_E2E_FLOW_CONTROL = 1 << 28,
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RING_FLAG_PCI_NO_SNOOP = 1 << 29,
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RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */
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RING_FLAG_ENABLE = 1 << 31,
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};
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enum ring_desc_flags {
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RING_DESC_ISOCH = 0x1, /* TX only? */
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RING_DESC_COMPLETED = 0x2, /* set by NHI */
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RING_DESC_POSTED = 0x4, /* always set this */
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RING_DESC_INTERRUPT = 0x8, /* request an interrupt on completion */
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};
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/**
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* struct ring_desc - TX/RX ring entry
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*
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* For TX set length/eof/sof.
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* For RX length/eof/sof are set by the NHI.
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*/
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struct ring_desc {
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u64 phys;
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u32 length:12;
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u32 eof:4;
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u32 sof:4;
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enum ring_desc_flags flags:12;
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u32 time; /* write zero */
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} __packed;
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/* NHI registers in bar 0 */
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/*
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* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: physical pointer to an array of struct ring_desc
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* 08: ring tail (set by NHI)
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* 10: ring head (index of first non posted descriptor)
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* 12: descriptor count
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*/
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#define REG_TX_RING_BASE 0x00000
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/*
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* 16 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: physical pointer to an array of struct ring_desc
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* 08: ring head (index of first not posted descriptor)
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* 10: ring tail (set by NHI)
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* 12: descriptor count
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* 14: max frame sizes (anything larger than 0x100 has no effect)
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*/
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#define REG_RX_RING_BASE 0x08000
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/*
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* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: enum_ring_flags
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* 04: isoch time stamp ?? (write 0)
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* ..: unknown
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*/
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#define REG_TX_OPTIONS_BASE 0x19800
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/*
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* 32 bytes per entry, one entry for every hop (REG_HOP_COUNT)
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* 00: enum ring_flags
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* If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
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* the corresponding TX hop id.
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* 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings)
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* ..: unknown
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*/
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#define REG_RX_OPTIONS_BASE 0x29800
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#define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12)
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#define REG_RX_OPTIONS_E2E_HOP_SHIFT 12
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/*
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* three bitfields: tx, rx, rx overflow
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* Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are
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* cleared on read. New interrupts are fired only after ALL registers have been
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* read (even those containing only disabled rings).
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*/
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#define REG_RING_NOTIFY_BASE 0x37800
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#define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32)
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/*
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* two bitfields: rx, tx
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* Both bitfields contains one bit for every hop (REG_HOP_COUNT). To
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* enable/disable interrupts set/clear the corresponding bits.
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*/
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#define REG_RING_INTERRUPT_BASE 0x38200
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#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
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#define REG_INT_THROTTLING_RATE 0x38c00
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/* Interrupt Vector Allocation */
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#define REG_INT_VEC_ALLOC_BASE 0x38c40
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#define REG_INT_VEC_ALLOC_BITS 4
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#define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0)
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#define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS)
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/* The last 11 bits contain the number of hops supported by the NHI port. */
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#define REG_HOP_COUNT 0x39640
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#define REG_DMA_MISC 0x39864
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#define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2)
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#define REG_INMAIL_DATA 0x39900
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#define REG_INMAIL_CMD 0x39904
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#define REG_INMAIL_CMD_MASK GENMASK(7, 0)
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#define REG_INMAIL_ERROR BIT(30)
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#define REG_INMAIL_OP_REQUEST BIT(31)
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#define REG_OUTMAIL_CMD 0x3990c
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#define REG_OUTMAIL_CMD_OPMODE_SHIFT 8
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#define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8)
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#define REG_FW_STS 0x39944
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#define REG_FW_STS_NVM_AUTH_DONE BIT(31)
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#define REG_FW_STS_CIO_RESET_REQ BIT(30)
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#define REG_FW_STS_ICM_EN_CPU BIT(2)
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#define REG_FW_STS_ICM_EN_INVERT BIT(1)
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#define REG_FW_STS_ICM_EN BIT(0)
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#endif
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