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c4cd4c168b
Currently we use vgic_irq_lr_map in order to track which LRs hold which
IRQs, and lr_used bitmap in order to track which LRs are used or free.
vgic_irq_lr_map is actually used only for piggy-back optimization, and
can be easily replaced by iteration over lr_used. This is good because in
future, when LPI support is introduced, number of IRQs will grow up to at
least 16384, while numbers from 1024 to 8192 are never going to be used.
This would be a huge memory waste.
In its turn, lr_used is also completely redundant since
ae705930fca6322600690df9dc1c7d0516145a93 ("arm/arm64: KVM: Keep elrsr/aisr
in sync with software model"), because together with lr_used we also update
elrsr. This allows to easily replace lr_used with elrsr, inverting all
conditions (because in elrsr '1' means 'free').
Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
275 lines
7.3 KiB
C
275 lines
7.3 KiB
C
/*
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* Copyright (C) 2012,2013 ARM Limited, All Rights Reserved.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/cpu.h>
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#include <linux/kvm.h>
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#include <linux/kvm_host.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_mmu.h>
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static struct vgic_lr vgic_v2_get_lr(const struct kvm_vcpu *vcpu, int lr)
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{
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struct vgic_lr lr_desc;
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u32 val = vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr];
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lr_desc.irq = val & GICH_LR_VIRTUALID;
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if (lr_desc.irq <= 15)
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lr_desc.source = (val >> GICH_LR_PHYSID_CPUID_SHIFT) & 0x7;
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else
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lr_desc.source = 0;
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lr_desc.state = 0;
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if (val & GICH_LR_PENDING_BIT)
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lr_desc.state |= LR_STATE_PENDING;
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if (val & GICH_LR_ACTIVE_BIT)
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lr_desc.state |= LR_STATE_ACTIVE;
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if (val & GICH_LR_EOI)
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lr_desc.state |= LR_EOI_INT;
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if (val & GICH_LR_HW) {
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lr_desc.state |= LR_HW;
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lr_desc.hwirq = (val & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT;
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}
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return lr_desc;
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}
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static void vgic_v2_set_lr(struct kvm_vcpu *vcpu, int lr,
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struct vgic_lr lr_desc)
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{
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u32 lr_val;
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lr_val = lr_desc.irq;
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if (lr_desc.state & LR_STATE_PENDING)
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lr_val |= GICH_LR_PENDING_BIT;
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if (lr_desc.state & LR_STATE_ACTIVE)
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lr_val |= GICH_LR_ACTIVE_BIT;
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if (lr_desc.state & LR_EOI_INT)
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lr_val |= GICH_LR_EOI;
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if (lr_desc.state & LR_HW) {
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lr_val |= GICH_LR_HW;
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lr_val |= (u32)lr_desc.hwirq << GICH_LR_PHYSID_CPUID_SHIFT;
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}
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if (lr_desc.irq < VGIC_NR_SGIS)
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lr_val |= (lr_desc.source << GICH_LR_PHYSID_CPUID_SHIFT);
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vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = lr_val;
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}
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static void vgic_v2_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
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struct vgic_lr lr_desc)
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{
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if (!(lr_desc.state & LR_STATE_MASK))
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vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr |= (1ULL << lr);
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else
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vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr &= ~(1ULL << lr);
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}
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static u64 vgic_v2_get_elrsr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr;
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}
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static u64 vgic_v2_get_eisr(const struct kvm_vcpu *vcpu)
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{
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return vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr;
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}
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static void vgic_v2_clear_eisr(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.vgic_cpu.vgic_v2.vgic_eisr = 0;
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}
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static u32 vgic_v2_get_interrupt_status(const struct kvm_vcpu *vcpu)
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{
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u32 misr = vcpu->arch.vgic_cpu.vgic_v2.vgic_misr;
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u32 ret = 0;
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if (misr & GICH_MISR_EOI)
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ret |= INT_STATUS_EOI;
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if (misr & GICH_MISR_U)
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ret |= INT_STATUS_UNDERFLOW;
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return ret;
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}
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static void vgic_v2_enable_underflow(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr |= GICH_HCR_UIE;
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}
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static void vgic_v2_disable_underflow(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr &= ~GICH_HCR_UIE;
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}
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static void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr = vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr;
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vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >> GICH_VMCR_CTRL_SHIFT;
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vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >> GICH_VMCR_ALIAS_BINPOINT_SHIFT;
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vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >> GICH_VMCR_BINPOINT_SHIFT;
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vmcrp->pmr = (vmcr & GICH_VMCR_PRIMASK_MASK) >> GICH_VMCR_PRIMASK_SHIFT;
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}
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static void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
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{
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u32 vmcr;
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vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
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vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) & GICH_VMCR_ALIAS_BINPOINT_MASK;
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vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) & GICH_VMCR_BINPOINT_MASK;
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vmcr |= (vmcrp->pmr << GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = vmcr;
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}
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static void vgic_v2_enable(struct kvm_vcpu *vcpu)
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{
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/*
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* By forcing VMCR to zero, the GIC will restore the binary
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* points to their reset values. Anything else resets to zero
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* anyway.
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*/
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vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
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vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
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/* Get the show on the road... */
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vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
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}
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static const struct vgic_ops vgic_v2_ops = {
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.get_lr = vgic_v2_get_lr,
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.set_lr = vgic_v2_set_lr,
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.sync_lr_elrsr = vgic_v2_sync_lr_elrsr,
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.get_elrsr = vgic_v2_get_elrsr,
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.get_eisr = vgic_v2_get_eisr,
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.clear_eisr = vgic_v2_clear_eisr,
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.get_interrupt_status = vgic_v2_get_interrupt_status,
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.enable_underflow = vgic_v2_enable_underflow,
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.disable_underflow = vgic_v2_disable_underflow,
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.get_vmcr = vgic_v2_get_vmcr,
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.set_vmcr = vgic_v2_set_vmcr,
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.enable = vgic_v2_enable,
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};
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static struct vgic_params vgic_v2_params;
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/**
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* vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
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* @node: pointer to the DT node
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* @ops: address of a pointer to the GICv2 operations
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* @params: address of a pointer to HW-specific parameters
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*
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* Returns 0 if a GICv2 has been found, with the low level operations
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* in *ops and the HW parameters in *params. Returns an error code
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* otherwise.
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*/
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int vgic_v2_probe(struct device_node *vgic_node,
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const struct vgic_ops **ops,
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const struct vgic_params **params)
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{
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int ret;
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struct resource vctrl_res;
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struct resource vcpu_res;
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struct vgic_params *vgic = &vgic_v2_params;
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vgic->maint_irq = irq_of_parse_and_map(vgic_node, 0);
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if (!vgic->maint_irq) {
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kvm_err("error getting vgic maintenance irq from DT\n");
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ret = -ENXIO;
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goto out;
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}
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ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
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if (ret) {
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kvm_err("Cannot obtain GICH resource\n");
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goto out;
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}
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vgic->vctrl_base = of_iomap(vgic_node, 2);
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if (!vgic->vctrl_base) {
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kvm_err("Cannot ioremap GICH\n");
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ret = -ENOMEM;
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goto out;
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}
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vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
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vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;
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ret = create_hyp_io_mappings(vgic->vctrl_base,
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vgic->vctrl_base + resource_size(&vctrl_res),
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vctrl_res.start);
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if (ret) {
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kvm_err("Cannot map VCTRL into hyp\n");
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goto out_unmap;
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}
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if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
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kvm_err("Cannot obtain GICV resource\n");
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ret = -ENXIO;
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goto out_unmap;
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}
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if (!PAGE_ALIGNED(vcpu_res.start)) {
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kvm_err("GICV physical address 0x%llx not page aligned\n",
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(unsigned long long)vcpu_res.start);
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ret = -ENXIO;
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goto out_unmap;
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}
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if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
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kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
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(unsigned long long)resource_size(&vcpu_res),
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PAGE_SIZE);
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ret = -ENXIO;
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goto out_unmap;
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}
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vgic->can_emulate_gicv2 = true;
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kvm_register_device_ops(&kvm_arm_vgic_v2_ops, KVM_DEV_TYPE_ARM_VGIC_V2);
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vgic->vcpu_base = vcpu_res.start;
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kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
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vctrl_res.start, vgic->maint_irq);
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vgic->type = VGIC_V2;
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vgic->max_gic_vcpus = VGIC_V2_MAX_CPUS;
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*ops = &vgic_v2_ops;
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*params = vgic;
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goto out;
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out_unmap:
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iounmap(vgic->vctrl_base);
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out:
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of_node_put(vgic_node);
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return ret;
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}
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