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cf67edce22
Xilinx ZynqMP SoC and the Arasan controller support 64-bit DMA addressing. Define the right mask otherwise the default is 32 and some accesses may overflow the default mask. Reported-by: Jorge Courett <jorge.courett@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Jorge Courett <jorge.courett@gmail.com> Link: https://lore.kernel.org/linux-mtd/20210527084548.208429-1-miquel.raynal@bootlin.com