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43c04ed791
Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg clock and reset controllers. These provide the base clocks and resets on the platform, enough to bring up all essential blocks including PWRAP, MSDC and peripherals (UART, I2C, SPI). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241017071708.38663-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
108 lines
4.6 KiB
C
108 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-infracfg.h>
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#include <dt-bindings/reset/mediatek,mt6735-infracfg.h>
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#define INFRA_RST0 0x30
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#define INFRA_GLOBALCON_PDN0 0x40
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#define INFRA_PDN1 0x44
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#define INFRA_PDN_STA 0x48
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#define RST_NR_PER_BANK 32
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static struct mtk_gate_regs infra_cg_regs = {
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.set_ofs = INFRA_GLOBALCON_PDN0,
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.clr_ofs = INFRA_PDN1,
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.sta_ofs = INFRA_PDN_STA,
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};
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static const struct mtk_gate infracfg_gates[] = {
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GATE_MTK(CLK_INFRA_DBG, "dbg", "axi_sel", &infra_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCE, "gce", "axi_sel", &infra_cg_regs, 1, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_TRBG, "trbg", "axi_sel", &infra_cg_regs, 2, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CPUM, "cpum", "axi_sel", &infra_cg_regs, 3, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_DEVAPC, "devapc", "axi_sel", &infra_cg_regs, 4, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_AUDIO, "audio", "aud_intbus_sel", &infra_cg_regs, 5, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_GCPU, "gcpu", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_L2C_SRAM, "l2csram", "axi_sel", &infra_cg_regs, 7, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CLDMA, "cldma", "axi_sel", &infra_cg_regs, 12, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CONNMCU_BUS, "connmcu_bus", "axi_sel", &infra_cg_regs, 15, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_KP, "kp", "axi_sel", &infra_cg_regs, 16, &mtk_clk_gate_ops_setclr),
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GATE_MTK_FLAGS(CLK_INFRA_APXGPT, "apxgpt", "axi_sel", &infra_cg_regs, 18, &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL),
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GATE_MTK(CLK_INFRA_SEJ, "sej", "axi_sel", &infra_cg_regs, 19, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF0_AP, "ccif0ap", "axi_sel", &infra_cg_regs, 20, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_CCIF1_AP, "ccif1ap", "axi_sel", &infra_cg_regs, 21, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_SPI, "pmicspi", "pmicspi_sel", &infra_cg_regs, 22, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_INFRA_PMIC_WRAP, "pmicwrap", "axi_sel", &infra_cg_regs, 23, &mtk_clk_gate_ops_setclr)
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};
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static u16 infracfg_rst_bank_ofs[] = { INFRA_RST0 };
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static u16 infracfg_rst_idx_map[] = {
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[MT6735_INFRA_RST0_EMI_REG] = 0 * RST_NR_PER_BANK + 0,
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[MT6735_INFRA_RST0_DRAMC0_AO] = 0 * RST_NR_PER_BANK + 1,
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[MT6735_INFRA_RST0_AP_CIRQ_EINT] = 0 * RST_NR_PER_BANK + 3,
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[MT6735_INFRA_RST0_APXGPT] = 0 * RST_NR_PER_BANK + 4,
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[MT6735_INFRA_RST0_SCPSYS] = 0 * RST_NR_PER_BANK + 5,
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[MT6735_INFRA_RST0_KP] = 0 * RST_NR_PER_BANK + 6,
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[MT6735_INFRA_RST0_PMIC_WRAP] = 0 * RST_NR_PER_BANK + 7,
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[MT6735_INFRA_RST0_CLDMA_AO_TOP] = 0 * RST_NR_PER_BANK + 8,
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[MT6735_INFRA_RST0_USBSIF_TOP] = 0 * RST_NR_PER_BANK + 9,
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[MT6735_INFRA_RST0_EMI] = 0 * RST_NR_PER_BANK + 16,
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[MT6735_INFRA_RST0_CCIF] = 0 * RST_NR_PER_BANK + 17,
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[MT6735_INFRA_RST0_DRAMC0] = 0 * RST_NR_PER_BANK + 18,
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[MT6735_INFRA_RST0_EMI_AO_REG] = 0 * RST_NR_PER_BANK + 19,
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[MT6735_INFRA_RST0_CCIF_AO] = 0 * RST_NR_PER_BANK + 20,
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[MT6735_INFRA_RST0_TRNG] = 0 * RST_NR_PER_BANK + 21,
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[MT6735_INFRA_RST0_SYS_CIRQ] = 0 * RST_NR_PER_BANK + 22,
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[MT6735_INFRA_RST0_GCE] = 0 * RST_NR_PER_BANK + 23,
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[MT6735_INFRA_RST0_M4U] = 0 * RST_NR_PER_BANK + 24,
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[MT6735_INFRA_RST0_CCIF1] = 0 * RST_NR_PER_BANK + 25,
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[MT6735_INFRA_RST0_CLDMA_TOP_PD] = 0 * RST_NR_PER_BANK + 26
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};
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static const struct mtk_clk_rst_desc infracfg_resets = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = infracfg_rst_bank_ofs,
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.rst_bank_nr = ARRAY_SIZE(infracfg_rst_bank_ofs),
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.rst_idx_map = infracfg_rst_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(infracfg_rst_idx_map)
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};
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static const struct mtk_clk_desc infracfg_clks = {
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.clks = infracfg_gates,
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.num_clks = ARRAY_SIZE(infracfg_gates),
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.rst_desc = &infracfg_resets
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};
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static const struct of_device_id of_match_mt6735_infracfg[] = {
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{ .compatible = "mediatek,mt6735-infracfg", .data = &infracfg_clks },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_mt6735_infracfg);
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static struct platform_driver clk_mt6735_infracfg = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-infracfg",
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.of_match_table = of_match_mt6735_infracfg,
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},
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};
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module_platform_driver(clk_mt6735_infracfg);
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MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
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MODULE_DESCRIPTION("MediaTek MT6735 infracfg clock and reset driver");
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MODULE_LICENSE("GPL");
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