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d8f64797c5
Many of the Tegra DT binding documents say nothing about the clocks or clock-names properties, yet those are present and required in DT files. This patch simply updates the documentation file to match the implicit definition of the binding, based on real-world DT content. All Tegra bindings that mention clocks are updated to have consistent wording and formatting of the clock-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
27 lines
963 B
Plaintext
27 lines
963 B
Plaintext
NVIDIA Tegra 20 AC97 controller
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Required properties:
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- compatible : "nvidia,tegra20-ac97"
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- reg : Should contain AC97 controller registers location and length
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- interrupts : Should contain AC97 interrupt
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- clocks : Must contain one entry, for the module clock.
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See ../clocks/clock-bindings.txt for details.
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- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
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request selector for the AC97 controller
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- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
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of the GPIO used to reset the external AC97 codec
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- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
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of the GPIO corresponding with the AC97 DAP _FS line
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Example:
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ac97@70002000 {
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compatible = "nvidia,tegra20-ac97";
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reg = <0x70002000 0x200>;
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interrupts = <0 81 0x04>;
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nvidia,dma-request-selector = <&apbdma 12>;
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nvidia,codec-reset-gpio = <&gpio 170 0>;
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nvidia,codec-sync-gpio = <&gpio 120 0>;
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clocks = <&tegra_car 3>;
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};
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