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ed852cde25
Our current Crystal Cove OpRegion driver is only valid for the
Crystal Cove PMIC variant found on Bay Trail (BYT) boards,
Cherry Trail (CHT) based boards use another variant.
At least the regulator registers are different on CHT and these registers
are one of the things controlled by the custom PMIC OpRegion.
Commit 4d9ed62ab142 ("mfd: intel_soc_pmic: Export separate mfd-cell
configs for BYT and CHT") has disabled the intel_pmic_crc.c code for CHT
devices by removing the "crystal_cove_pmic" MFD cell on CHT devices.
This commit renames the intel_pmic_crc.c driver and the cell to be
prefixed with "byt" to indicate that this code is for BYT devices only.
This is a preparation patch for adding a separate PMIC OpRegion
driver for the CHT variant of the Crystal Cove PMIC (sometimes called
Crystal Cove Plus in Android kernel sources).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
138 lines
3.7 KiB
C
138 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device access for Crystal Cove PMIC
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*
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* Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
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*
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* Author: Yang, Bin <bin.yang@intel.com>
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* Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include "intel_soc_pmic_core.h"
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#define CRYSTAL_COVE_MAX_REGISTER 0xC6
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#define CRYSTAL_COVE_REG_IRQLVL1 0x02
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#define CRYSTAL_COVE_REG_MIRQLVL1 0x0E
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#define CRYSTAL_COVE_IRQ_PWRSRC 0
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#define CRYSTAL_COVE_IRQ_THRM 1
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#define CRYSTAL_COVE_IRQ_BCU 2
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#define CRYSTAL_COVE_IRQ_ADC 3
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#define CRYSTAL_COVE_IRQ_CHGR 4
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#define CRYSTAL_COVE_IRQ_GPIO 5
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#define CRYSTAL_COVE_IRQ_VHDMIOCP 6
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static struct resource gpio_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
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};
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static struct resource pwrsrc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
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};
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static struct resource adc_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
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};
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static struct resource thermal_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
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};
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static struct resource bcu_resources[] = {
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DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
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};
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static struct mfd_cell crystal_cove_byt_dev[] = {
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{
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.name = "crystal_cove_pwrsrc",
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.num_resources = ARRAY_SIZE(pwrsrc_resources),
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.resources = pwrsrc_resources,
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},
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{
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.name = "crystal_cove_adc",
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.num_resources = ARRAY_SIZE(adc_resources),
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.resources = adc_resources,
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},
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{
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.name = "crystal_cove_thermal",
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.num_resources = ARRAY_SIZE(thermal_resources),
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.resources = thermal_resources,
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},
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{
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.name = "crystal_cove_bcu",
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.num_resources = ARRAY_SIZE(bcu_resources),
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.resources = bcu_resources,
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},
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "byt_crystal_cove_pmic",
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static struct mfd_cell crystal_cove_cht_dev[] = {
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{
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.name = "crystal_cove_gpio",
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.num_resources = ARRAY_SIZE(gpio_resources),
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.resources = gpio_resources,
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},
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{
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.name = "crystal_cove_pwm",
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},
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};
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static const struct regmap_config crystal_cove_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = CRYSTAL_COVE_MAX_REGISTER,
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.cache_type = REGCACHE_NONE,
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};
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static const struct regmap_irq crystal_cove_irqs[] = {
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
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REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
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};
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static const struct regmap_irq_chip crystal_cove_irq_chip = {
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.name = "Crystal Cove",
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.irqs = crystal_cove_irqs,
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.num_irqs = ARRAY_SIZE(crystal_cove_irqs),
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.num_regs = 1,
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.status_base = CRYSTAL_COVE_REG_IRQLVL1,
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.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_byt_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
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.irq_flags = IRQF_TRIGGER_RISING,
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.cell_dev = crystal_cove_cht_dev,
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.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
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.regmap_config = &crystal_cove_regmap_config,
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.irq_chip = &crystal_cove_irq_chip,
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};
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