Timo Alho a47b44fbb1 clk: tegra: fix error return case for recalc_rate ...

tegra-bpmp clocks driver makes implicit conversion of signed error
code to unsigned value in recalc_rate operation. The behavior for
recalc_rate, according to it's specification, should be that "If the
driver cannot figure out a rate for this clock, it must return 0."

Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver")
Signed-off-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20230912112951.2330497-1-cyndis@kapsi.fi
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2023-09-12 10:56:05 -07:00

..

clk-audio-sync.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-bpmp.c

clk: tegra: fix error return case for recalc_rate

2023-09-12 10:56:05 -07:00

clk-device.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-dfll.c

clk: tegra: Don't warn three times about failure to unregister

2023-03-28 19:23:35 -07:00

clk-dfll.h

clk: tegra: clk-dfll: Add suspend and resume support

2019-11-11 14:53:03 +01:00

clk-divider.c

clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation

2020-01-10 15:50:05 +01:00

clk-id.h

clk: tegra: Fix duplicated SE clock entry

2020-12-10 12:51:59 -08:00

clk-periph-fixed.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-periph-gate.c

clk: tegra: Don't deassert reset on enabling clocks

2021-05-31 15:16:46 +02:00

clk-periph.c

clk: tegra: periph: Switch to determine_rate

2023-06-08 18:39:35 -07:00

clk-pll-out.c

clk: tegra: pllout: Save and restore pllout context

2019-11-11 14:53:02 +01:00

clk-pll.c

clk: tegra: Support runtime PM and power domain

2021-12-15 18:55:21 +01:00

clk-sdmmc-mux.c

clk: tegra: Implement disable_unused() of tegra_clk_sdmmc_mux_ops

2021-07-27 14:54:19 -07:00

clk-super.c

clk: tegra: super: Switch to determine_rate

2023-06-08 18:39:35 -07:00

clk-tegra20-emc.c

clk: tegra: Export Tegra20 EMC kernel symbols

2020-11-06 19:24:04 +01:00

clk-tegra20.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-tegra30.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-tegra114.c

clk: tegra: Fix Tegra PWM parent clock

2022-10-14 13:44:24 -07:00

clk-tegra124-dfll-fcpu.c

clk: Explicitly include correct DT includes

2023-07-19 13:13:16 -07:00

clk-tegra124-emc.c

clk: tegra: tegra124-emc: Fix potential memory leak

2023-06-14 18:25:51 -07:00

clk-tegra124.c

clk: tegra: Fix Tegra PWM parent clock

2022-10-14 13:44:24 -07:00

clk-tegra210-emc.c

This pull request contains zero diff to the core framework. It is a collection

2020-10-22 12:53:28 -07:00

clk-tegra210.c

clk: tegra: Fix Tegra PWM parent clock

2022-10-14 13:44:24 -07:00

clk-tegra-audio.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-tegra-fixed.c

clk: tegra: Remove CLK_M_DIV fixed clocks

2020-03-12 11:33:32 +01:00

clk-tegra-periph.c

clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock

2021-08-11 11:57:01 +02:00

clk-tegra-super-cclk.c

clk: tegra: Avoid calling an uninitialized function

2023-07-04 08:54:37 -07:00

clk-tegra-super-gen4.c

clk: tegra: clk-super: Fix to enable PLLP branches to CPU

2019-11-11 14:53:03 +01:00

clk-utils.c

clk: tegra: Refactor fractional divider calculation

2018-07-25 13:43:34 -07:00

clk.c

Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next

2023-08-30 14:38:19 -07:00

clk.h

clk: tegra: Support runtime PM and power domain

2021-12-15 18:55:21 +01:00

cvb.c

clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param

2021-02-11 11:56:05 -08:00

cvb.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174

2019-05-30 11:26:41 -07:00

Kconfig

memory: tegra124-emc: Make driver modular

2021-01-05 18:00:09 +01:00

Makefile

clk: tegra: Support runtime PM and power domain

2021-12-15 18:55:21 +01:00