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737af37e9c
Added dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Piyush Mehta <piyush.mehta@amd.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230721041119.4058430-2-piyush.mehta@amd.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
54 lines
1.4 KiB
YAML
54 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Zynq UltraScale+ MPSoC and Versal reset
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maintainers:
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- Piyush Mehta <piyush.mehta@amd.com>
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description: |
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The Zynq UltraScale+ MPSoC and Versal has several different resets.
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The PS reset subsystem is responsible for handling the external reset
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input to the device and that all internal reset requirements are met
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for the system (as a whole) and for the functional units.
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Please also refer to reset.txt in this directory for common reset
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controller binding usage. Device nodes that need access to reset
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lines should specify them as a reset phandle in their corresponding
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node as specified in reset.txt.
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For list of all valid reset indices for Zynq UltraScale+ MPSoC
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<dt-bindings/reset/xlnx-zynqmp-resets.h>
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For list of all valid reset indices for Versal
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<dt-bindings/reset/xlnx-versal-resets.h>
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properties:
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compatible:
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enum:
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- xlnx,zynqmp-reset
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- xlnx,versal-reset
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- xlnx,versal-net-reset
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"#reset-cells":
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const: 1
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required:
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- compatible
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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zynqmp_reset: reset-controller {
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compatible = "xlnx,zynqmp-reset";
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#reset-cells = <1>;
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};
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...
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