mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-12 00:38:55 +00:00
f412384e2d
Raplace all calls to __raw_writel() with writel_relaxed(). It's safe to do as there's no endianness conversion being done in the code. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
151 lines
4.3 KiB
C
151 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
//
|
|
// Copyright (C) 2006, 2019 Texas Instruments.
|
|
//
|
|
// Interrupt handler for DaVinci boards.
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/io.h>
|
|
#include <linux/irqdomain.h>
|
|
|
|
#include <mach/hardware.h>
|
|
#include <mach/cputype.h>
|
|
#include <mach/common.h>
|
|
#include <asm/mach/irq.h>
|
|
#include <asm/exception.h>
|
|
|
|
#include "irqs.h"
|
|
|
|
#define DAVINCI_AINTC_FIQ_REG0 0x00
|
|
#define DAVINCI_AINTC_FIQ_REG1 0x04
|
|
#define DAVINCI_AINTC_IRQ_REG0 0x08
|
|
#define DAVINCI_AINTC_IRQ_REG1 0x0c
|
|
#define DAVINCI_AINTC_IRQ_IRQENTRY 0x14
|
|
#define DAVINCI_AINTC_IRQ_ENT_REG0 0x18
|
|
#define DAVINCI_AINTC_IRQ_ENT_REG1 0x1c
|
|
#define DAVINCI_AINTC_IRQ_INCTL_REG 0x20
|
|
#define DAVINCI_AINTC_IRQ_EABASE_REG 0x24
|
|
#define DAVINCI_AINTC_IRQ_INTPRI0_REG 0x30
|
|
#define DAVINCI_AINTC_IRQ_INTPRI7_REG 0x4c
|
|
|
|
static void __iomem *davinci_aintc_base;
|
|
static struct irq_domain *davinci_aintc_irq_domain;
|
|
|
|
static inline void davinci_aintc_writel(unsigned long value, int offset)
|
|
{
|
|
writel_relaxed(value, davinci_aintc_base + offset);
|
|
}
|
|
|
|
static inline unsigned long davinci_aintc_readl(int offset)
|
|
{
|
|
return readl_relaxed(davinci_aintc_base + offset);
|
|
}
|
|
|
|
static __init void
|
|
davinci_aintc_setup_gc(void __iomem *base,
|
|
unsigned int irq_start, unsigned int num)
|
|
{
|
|
struct irq_chip_generic *gc;
|
|
struct irq_chip_type *ct;
|
|
|
|
gc = irq_get_domain_generic_chip(davinci_aintc_irq_domain, irq_start);
|
|
gc->reg_base = base;
|
|
gc->irq_base = irq_start;
|
|
|
|
ct = gc->chip_types;
|
|
ct->chip.irq_ack = irq_gc_ack_set_bit;
|
|
ct->chip.irq_mask = irq_gc_mask_clr_bit;
|
|
ct->chip.irq_unmask = irq_gc_mask_set_bit;
|
|
|
|
ct->regs.ack = DAVINCI_AINTC_IRQ_REG0;
|
|
ct->regs.mask = DAVINCI_AINTC_IRQ_ENT_REG0;
|
|
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
|
}
|
|
|
|
static asmlinkage void __exception_irq_entry
|
|
davinci_aintc_handle_irq(struct pt_regs *regs)
|
|
{
|
|
int irqnr = davinci_aintc_readl(DAVINCI_AINTC_IRQ_IRQENTRY);
|
|
|
|
/*
|
|
* Use the formula for entry vector index generation from section
|
|
* 8.3.3 of the manual.
|
|
*/
|
|
irqnr >>= 2;
|
|
irqnr -= 1;
|
|
|
|
handle_domain_irq(davinci_aintc_irq_domain, irqnr, regs);
|
|
}
|
|
|
|
/* ARM Interrupt Controller Initialization */
|
|
void __init davinci_aintc_init(void)
|
|
{
|
|
unsigned i, j;
|
|
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
|
|
int ret, irq_base;
|
|
|
|
davinci_aintc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
|
|
if (WARN_ON(!davinci_aintc_base))
|
|
return;
|
|
|
|
/* Clear all interrupt requests */
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
|
|
|
|
/* Disable all interrupts */
|
|
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG0);
|
|
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_ENT_REG1);
|
|
|
|
/* Interrupts disabled immediately, IRQ entry reflects all */
|
|
davinci_aintc_writel(0x0, DAVINCI_AINTC_IRQ_INCTL_REG);
|
|
|
|
/* we don't use the hardware vector table, just its entry addresses */
|
|
davinci_aintc_writel(0, DAVINCI_AINTC_IRQ_EABASE_REG);
|
|
|
|
/* Clear all interrupt requests */
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG0);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_FIQ_REG1);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG0);
|
|
davinci_aintc_writel(~0x0, DAVINCI_AINTC_IRQ_REG1);
|
|
|
|
for (i = DAVINCI_AINTC_IRQ_INTPRI0_REG;
|
|
i <= DAVINCI_AINTC_IRQ_INTPRI7_REG; i += 4) {
|
|
u32 pri;
|
|
|
|
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
|
|
pri |= (*davinci_def_priorities & 0x07) << j;
|
|
davinci_aintc_writel(pri, i);
|
|
}
|
|
|
|
irq_base = irq_alloc_descs(-1, 0, davinci_soc_info.intc_irq_num, 0);
|
|
if (WARN_ON(irq_base < 0))
|
|
return;
|
|
|
|
davinci_aintc_irq_domain = irq_domain_add_legacy(NULL,
|
|
davinci_soc_info.intc_irq_num,
|
|
irq_base, 0, &irq_domain_simple_ops,
|
|
NULL);
|
|
if (WARN_ON(!davinci_aintc_irq_domain))
|
|
return;
|
|
|
|
ret = irq_alloc_domain_generic_chips(davinci_aintc_irq_domain, 32, 1,
|
|
"AINTC", handle_edge_irq,
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0, 0);
|
|
if (WARN_ON(ret))
|
|
return;
|
|
|
|
for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num;
|
|
i += 32, j += 0x04)
|
|
davinci_aintc_setup_gc(davinci_aintc_base + j,
|
|
irq_base + i, 32);
|
|
|
|
irq_set_handler(DAVINCI_INTC_IRQ(IRQ_TINT1_TINT34), handle_level_irq);
|
|
set_handle_irq(davinci_aintc_handle_irq);
|
|
}
|