2019-06-01 08:08:55 +00:00
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// SPDX-License-Identifier: GPL-2.0-only
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2012-05-12 08:36:38 +00:00
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/*
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* Driver for Texas Instruments INA219, INA226 power monitor chips
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*
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* INA219:
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* Zero Drift Bi-Directional Current/Power Monitor with I2C Interface
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2020-07-19 18:15:30 +00:00
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* Datasheet: https://www.ti.com/product/ina219
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2012-05-12 08:36:38 +00:00
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*
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2012-05-12 18:33:11 +00:00
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* INA220:
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* Bi-Directional Current/Power Monitor with I2C Interface
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2020-07-19 18:15:30 +00:00
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* Datasheet: https://www.ti.com/product/ina220
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2012-05-12 18:33:11 +00:00
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*
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2012-05-12 08:36:38 +00:00
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* INA226:
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* Bi-Directional Current/Power Monitor with I2C Interface
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2020-07-19 18:15:30 +00:00
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* Datasheet: https://www.ti.com/product/ina226
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2012-05-12 08:36:38 +00:00
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*
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2012-05-12 18:33:11 +00:00
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* INA230:
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* Bi-directional Current/Power Monitor with I2C Interface
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2020-07-19 18:15:30 +00:00
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* Datasheet: https://www.ti.com/product/ina230
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2012-05-12 18:33:11 +00:00
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*
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2018-08-14 07:09:37 +00:00
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* Copyright (C) 2012 Lothar Felten <lothar.felten@gmail.com>
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2012-05-12 08:36:38 +00:00
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* Thanks to Jan Volkering
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*/
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2024-07-23 20:25:31 +00:00
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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2024-07-23 20:21:12 +00:00
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#include <linux/delay.h>
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2024-07-25 05:41:16 +00:00
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#include <linux/device.h>
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2012-05-12 08:36:38 +00:00
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#include <linux/err.h>
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#include <linux/hwmon.h>
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2024-07-23 20:21:12 +00:00
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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2024-07-23 20:23:30 +00:00
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#include <linux/property.h>
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2015-10-28 11:04:53 +00:00
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#include <linux/regmap.h>
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2024-07-23 20:21:12 +00:00
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#include <linux/slab.h>
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2024-07-25 05:41:16 +00:00
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#include <linux/sysfs.h>
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2024-07-23 20:21:12 +00:00
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#include <linux/util_macros.h>
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2012-05-12 08:36:38 +00:00
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/* common register definitions */
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#define INA2XX_CONFIG 0x00
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#define INA2XX_SHUNT_VOLTAGE 0x01 /* readonly */
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#define INA2XX_BUS_VOLTAGE 0x02 /* readonly */
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#define INA2XX_POWER 0x03 /* readonly */
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#define INA2XX_CURRENT 0x04 /* readonly */
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#define INA2XX_CALIBRATION 0x05
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/* INA226 register definitions */
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#define INA226_MASK_ENABLE 0x06
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#define INA226_ALERT_LIMIT 0x07
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#define INA226_DIE_ID 0xFF
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2024-11-06 15:05:46 +00:00
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/* SY24655 register definitions */
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#define SY24655_EIN 0x0A
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#define SY24655_ACCUM_CONFIG 0x0D
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#define INA2XX_MAX_REGISTERS 0x0D
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2012-05-12 08:36:38 +00:00
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/* settings - depend on use case */
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#define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */
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#define INA226_CONFIG_DEFAULT 0x4527 /* averages=16 */
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2024-08-27 17:23:10 +00:00
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#define INA260_CONFIG_DEFAULT 0x6527 /* averages=16 */
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2024-11-06 15:05:46 +00:00
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#define SY24655_CONFIG_DEFAULT 0x4527 /* averages=16 */
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/* (only for sy24655) */
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#define SY24655_ACCUM_CONFIG_DEFAULT 0x044C /* continuous mode, clear after read*/
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2012-05-12 08:36:38 +00:00
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/* worst case is 68.10 ms (~14.6Hz, ina219) */
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#define INA2XX_CONVERSION_RATE 15
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2015-01-05 14:20:52 +00:00
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#define INA2XX_MAX_DELAY 69 /* worst case delay in ms */
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#define INA2XX_RSHUNT_DEFAULT 10000
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2024-08-27 17:23:10 +00:00
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#define INA260_RSHUNT 2000
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2012-05-12 08:36:38 +00:00
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2015-01-09 16:03:42 +00:00
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/* bit mask for reading the averaging setting in the configuration register */
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2024-07-23 20:25:31 +00:00
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#define INA226_AVG_RD_MASK GENMASK(11, 9)
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2015-01-09 16:03:42 +00:00
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2024-07-23 20:25:31 +00:00
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#define INA226_READ_AVG(reg) FIELD_GET(INA226_AVG_RD_MASK, reg)
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2015-01-09 16:03:42 +00:00
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2024-07-23 23:17:02 +00:00
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#define INA226_ALERT_LATCH_ENABLE BIT(0)
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2024-07-24 16:31:08 +00:00
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#define INA226_ALERT_POLARITY BIT(1)
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2024-06-11 09:36:26 +00:00
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2020-05-05 00:59:45 +00:00
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/* bit number of alert functions in Mask/Enable Register */
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2024-07-23 20:25:31 +00:00
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#define INA226_SHUNT_OVER_VOLTAGE_MASK BIT(15)
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#define INA226_SHUNT_UNDER_VOLTAGE_MASK BIT(14)
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#define INA226_BUS_OVER_VOLTAGE_MASK BIT(13)
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#define INA226_BUS_UNDER_VOLTAGE_MASK BIT(12)
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#define INA226_POWER_OVER_LIMIT_MASK BIT(11)
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2020-05-05 00:59:45 +00:00
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/* bit mask for alert config bits of Mask/Enable Register */
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2024-07-23 20:25:31 +00:00
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#define INA226_ALERT_CONFIG_MASK GENMASK(15, 10)
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2020-05-05 00:59:45 +00:00
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#define INA226_ALERT_FUNCTION_FLAG BIT(4)
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2015-01-09 16:03:42 +00:00
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/*
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* Both bus voltage and shunt voltage conversion times for ina226 are set
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* to 0b0100 on POR, which translates to 2200 microseconds in total.
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*/
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#define INA226_TOTAL_CONV_TIME_DEFAULT 2200
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hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
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static bool ina2xx_writeable_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case INA2XX_CONFIG:
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case INA2XX_CALIBRATION:
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case INA226_MASK_ENABLE:
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case INA226_ALERT_LIMIT:
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2024-11-06 15:05:46 +00:00
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case SY24655_ACCUM_CONFIG:
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hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
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return true;
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default:
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return false;
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}
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}
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static bool ina2xx_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case INA2XX_SHUNT_VOLTAGE:
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case INA2XX_BUS_VOLTAGE:
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case INA2XX_POWER:
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case INA2XX_CURRENT:
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return true;
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default:
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return false;
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}
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}
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2024-08-01 23:43:03 +00:00
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static const struct regmap_config ina2xx_regmap_config = {
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2015-10-28 11:04:53 +00:00
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.reg_bits = 8,
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.val_bits = 16,
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hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
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.use_single_write = true,
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.use_single_read = true,
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2024-08-01 23:43:03 +00:00
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.max_register = INA2XX_MAX_REGISTERS,
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hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
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.cache_type = REGCACHE_MAPLE,
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.volatile_reg = ina2xx_volatile_reg,
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.writeable_reg = ina2xx_writeable_reg,
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2015-10-28 11:04:53 +00:00
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};
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2024-11-06 15:05:46 +00:00
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enum ina2xx_ids { ina219, ina226, ina260, sy24655 };
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2012-05-12 08:36:38 +00:00
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2012-05-12 18:21:01 +00:00
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struct ina2xx_config {
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u16 config_default;
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2024-08-27 19:57:10 +00:00
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bool has_alerts; /* chip supports alerts and limits */
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2024-08-27 17:23:10 +00:00
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bool has_ishunt; /* chip has internal shunt resistor */
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2024-11-06 15:05:46 +00:00
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bool has_power_average; /* chip has internal shunt resistor */
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2017-11-22 15:32:15 +00:00
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int calibration_value;
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2012-05-12 18:21:01 +00:00
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int shunt_div;
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int bus_voltage_shift;
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int bus_voltage_lsb; /* uV */
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2017-11-22 15:32:15 +00:00
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int power_lsb_factor;
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2012-05-12 18:21:01 +00:00
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};
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2012-05-12 08:36:38 +00:00
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struct ina2xx_data {
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2012-05-12 18:21:01 +00:00
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const struct ina2xx_config *config;
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2024-07-24 16:31:08 +00:00
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enum ina2xx_ids chip;
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2012-05-12 08:36:38 +00:00
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2015-01-05 14:20:52 +00:00
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long rshunt;
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2017-11-22 15:32:15 +00:00
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long current_lsb_uA;
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long power_lsb_uW;
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2015-10-28 11:04:53 +00:00
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struct mutex config_lock;
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struct regmap *regmap;
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2024-11-06 15:05:46 +00:00
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struct i2c_client *client;
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2012-05-12 08:36:38 +00:00
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};
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2012-05-12 18:21:01 +00:00
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static const struct ina2xx_config ina2xx_config[] = {
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[ina219] = {
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.config_default = INA219_CONFIG_DEFAULT,
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2017-11-22 15:32:15 +00:00
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.calibration_value = 4096,
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2012-05-12 18:21:01 +00:00
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.shunt_div = 100,
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.bus_voltage_shift = 3,
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.bus_voltage_lsb = 4000,
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2017-11-22 15:32:15 +00:00
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.power_lsb_factor = 20,
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2024-08-27 19:57:10 +00:00
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.has_alerts = false,
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2024-08-27 17:23:10 +00:00
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.has_ishunt = false,
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2024-11-06 15:05:46 +00:00
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.has_power_average = false,
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2012-05-12 18:21:01 +00:00
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},
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[ina226] = {
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.config_default = INA226_CONFIG_DEFAULT,
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2017-11-22 15:32:15 +00:00
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.calibration_value = 2048,
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2012-05-12 18:21:01 +00:00
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.shunt_div = 400,
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.bus_voltage_shift = 0,
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.bus_voltage_lsb = 1250,
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2017-11-22 15:32:15 +00:00
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.power_lsb_factor = 25,
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2024-08-27 19:57:10 +00:00
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.has_alerts = true,
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2024-08-27 17:23:10 +00:00
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.has_ishunt = false,
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2024-11-06 15:05:46 +00:00
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.has_power_average = false,
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2024-08-27 17:23:10 +00:00
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},
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[ina260] = {
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.config_default = INA260_CONFIG_DEFAULT,
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.shunt_div = 400,
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.bus_voltage_shift = 0,
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.bus_voltage_lsb = 1250,
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.power_lsb_factor = 8,
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.has_alerts = true,
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.has_ishunt = true,
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2024-11-06 15:05:46 +00:00
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.has_power_average = false,
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},
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[sy24655] = {
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.config_default = SY24655_CONFIG_DEFAULT,
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.calibration_value = 4096,
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.shunt_div = 400,
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.bus_voltage_shift = 0,
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.bus_voltage_lsb = 1250,
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.power_lsb_factor = 25,
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.has_alerts = true,
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.has_ishunt = false,
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.has_power_average = true,
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2012-05-12 18:21:01 +00:00
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},
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};
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2015-01-09 16:03:42 +00:00
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/*
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* Available averaging rates for ina226. The indices correspond with
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* the bit values expected by the chip (according to the ina226 datasheet,
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* table 3 AVG bit settings, found at
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2020-07-19 18:15:30 +00:00
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* https://www.ti.com/lit/ds/symlink/ina226.pdf.
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2015-01-09 16:03:42 +00:00
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*/
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static const int ina226_avg_tab[] = { 1, 4, 16, 64, 128, 256, 512, 1024 };
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|
|
|
static int ina226_reg_to_interval(u16 config)
|
|
|
|
{
|
|
|
|
int avg = ina226_avg_tab[INA226_READ_AVG(config)];
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Multiply the total conversion time by the number of averages.
|
|
|
|
* Return the result in milliseconds.
|
|
|
|
*/
|
|
|
|
return DIV_ROUND_CLOSEST(avg * INA226_TOTAL_CONV_TIME_DEFAULT, 1000);
|
|
|
|
}
|
|
|
|
|
2015-10-28 11:04:53 +00:00
|
|
|
/*
|
|
|
|
* Return the new, shifted AVG field value of CONFIG register,
|
|
|
|
* to use with regmap_update_bits
|
|
|
|
*/
|
2024-07-25 05:41:16 +00:00
|
|
|
static u16 ina226_interval_to_reg(long interval)
|
2015-01-09 16:03:42 +00:00
|
|
|
{
|
|
|
|
int avg, avg_bits;
|
|
|
|
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
/*
|
|
|
|
* The maximum supported interval is 1,024 * (2 * 8.244ms) ~= 16.8s.
|
|
|
|
* Clamp to 32 seconds before calculations to avoid overflows.
|
|
|
|
*/
|
|
|
|
interval = clamp_val(interval, 0, 32000);
|
|
|
|
|
2015-01-09 16:03:42 +00:00
|
|
|
avg = DIV_ROUND_CLOSEST(interval * 1000,
|
|
|
|
INA226_TOTAL_CONV_TIME_DEFAULT);
|
2015-04-16 19:43:34 +00:00
|
|
|
avg_bits = find_closest(avg, ina226_avg_tab,
|
|
|
|
ARRAY_SIZE(ina226_avg_tab));
|
2015-01-09 16:03:42 +00:00
|
|
|
|
2024-07-23 20:25:31 +00:00
|
|
|
return FIELD_PREP(INA226_AVG_RD_MASK, avg_bits);
|
2015-01-09 16:03:42 +00:00
|
|
|
}
|
|
|
|
|
2024-08-01 22:34:48 +00:00
|
|
|
static int ina2xx_get_value(struct ina2xx_data *data, u8 reg,
|
|
|
|
unsigned int regval)
|
|
|
|
{
|
|
|
|
int val;
|
|
|
|
|
|
|
|
switch (reg) {
|
|
|
|
case INA2XX_SHUNT_VOLTAGE:
|
|
|
|
/* signed register */
|
|
|
|
val = DIV_ROUND_CLOSEST((s16)regval, data->config->shunt_div);
|
|
|
|
break;
|
|
|
|
case INA2XX_BUS_VOLTAGE:
|
|
|
|
val = (regval >> data->config->bus_voltage_shift) *
|
|
|
|
data->config->bus_voltage_lsb;
|
|
|
|
val = DIV_ROUND_CLOSEST(val, 1000);
|
|
|
|
break;
|
|
|
|
case INA2XX_POWER:
|
|
|
|
val = regval * data->power_lsb_uW;
|
|
|
|
break;
|
|
|
|
case INA2XX_CURRENT:
|
|
|
|
/* signed register, result in mA */
|
|
|
|
val = (s16)regval * data->current_lsb_uA;
|
|
|
|
val = DIV_ROUND_CLOSEST(val, 1000);
|
|
|
|
break;
|
|
|
|
case INA2XX_CALIBRATION:
|
|
|
|
val = regval;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* programmer goofed */
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
val = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return val;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
/*
|
|
|
|
* Read and convert register value from chip. If the register value is 0,
|
|
|
|
* check if the chip has been power cycled or reset. If so, re-initialize it.
|
|
|
|
*/
|
|
|
|
static int ina2xx_read_init(struct device *dev, int reg, long *val)
|
2015-01-05 14:20:52 +00:00
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
2024-08-01 21:57:39 +00:00
|
|
|
struct regmap *regmap = data->regmap;
|
2024-07-25 05:41:16 +00:00
|
|
|
unsigned int regval;
|
2015-10-28 11:04:53 +00:00
|
|
|
int ret, retry;
|
2012-05-12 08:36:38 +00:00
|
|
|
|
2024-08-27 17:23:10 +00:00
|
|
|
if (data->config->has_ishunt) {
|
|
|
|
/* No calibration needed */
|
|
|
|
ret = regmap_read(regmap, reg, ®val);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
*val = ina2xx_get_value(data, reg, regval);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-05 14:20:52 +00:00
|
|
|
for (retry = 5; retry; retry--) {
|
2024-07-25 05:41:16 +00:00
|
|
|
ret = regmap_read(regmap, reg, ®val);
|
2015-10-28 11:04:53 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2015-01-05 14:20:52 +00:00
|
|
|
/*
|
|
|
|
* If the current value in the calibration register is 0, the
|
|
|
|
* power and current registers will also remain at 0. In case
|
|
|
|
* the chip has been reset let's check the calibration
|
|
|
|
* register and reinitialize if needed.
|
2015-10-28 11:04:53 +00:00
|
|
|
* We do that extra read of the calibration register if there
|
|
|
|
* is some hint of a chip reset.
|
2015-01-05 14:20:52 +00:00
|
|
|
*/
|
2024-07-25 05:41:16 +00:00
|
|
|
if (regval == 0) {
|
2015-10-28 11:04:53 +00:00
|
|
|
unsigned int cal;
|
|
|
|
|
hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
|
|
|
ret = regmap_read_bypassed(regmap, INA2XX_CALIBRATION, &cal);
|
2015-10-28 11:04:53 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (cal == 0) {
|
|
|
|
dev_warn(dev, "chip not calibrated, reinitializing\n");
|
|
|
|
|
hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
|
|
|
regcache_mark_dirty(regmap);
|
|
|
|
regcache_sync(regmap);
|
|
|
|
|
2015-10-28 11:04:53 +00:00
|
|
|
/*
|
|
|
|
* Let's make sure the power and current
|
|
|
|
* registers have been updated before trying
|
|
|
|
* again.
|
|
|
|
*/
|
|
|
|
msleep(INA2XX_MAX_DELAY);
|
|
|
|
continue;
|
|
|
|
}
|
2015-01-05 14:20:52 +00:00
|
|
|
}
|
2024-07-25 05:41:16 +00:00
|
|
|
*val = ina2xx_get_value(data, reg, regval);
|
2015-01-05 14:20:52 +00:00
|
|
|
return 0;
|
2012-05-12 08:36:38 +00:00
|
|
|
}
|
2015-01-05 14:20:52 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we're here then although all write operations succeeded, the
|
|
|
|
* chip still returns 0 in the calibration register. Nothing more we
|
|
|
|
* can do here.
|
|
|
|
*/
|
|
|
|
dev_err(dev, "unable to reinitialize the chip\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2020-05-05 00:59:45 +00:00
|
|
|
/*
|
|
|
|
* Turns alert limit values into register values.
|
|
|
|
* Opposite of the formula in ina2xx_get_value().
|
|
|
|
*/
|
2024-08-28 22:23:53 +00:00
|
|
|
static u16 ina226_alert_to_reg(struct ina2xx_data *data, int reg, long val)
|
2020-05-05 00:59:45 +00:00
|
|
|
{
|
2024-08-28 22:18:51 +00:00
|
|
|
switch (reg) {
|
|
|
|
case INA2XX_SHUNT_VOLTAGE:
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
val = clamp_val(val, 0, SHRT_MAX * data->config->shunt_div);
|
2020-05-05 00:59:45 +00:00
|
|
|
val *= data->config->shunt_div;
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
return clamp_val(val, 0, SHRT_MAX);
|
2024-08-28 22:18:51 +00:00
|
|
|
case INA2XX_BUS_VOLTAGE:
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
val = clamp_val(val, 0, 200000);
|
2020-05-05 00:59:45 +00:00
|
|
|
val = (val * 1000) << data->config->bus_voltage_shift;
|
|
|
|
val = DIV_ROUND_CLOSEST(val, data->config->bus_voltage_lsb);
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
return clamp_val(val, 0, USHRT_MAX);
|
2024-08-28 22:18:51 +00:00
|
|
|
case INA2XX_POWER:
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
val = clamp_val(val, 0, UINT_MAX - data->power_lsb_uW);
|
2020-05-05 00:59:45 +00:00
|
|
|
val = DIV_ROUND_CLOSEST(val, data->power_lsb_uW);
|
|
|
|
return clamp_val(val, 0, USHRT_MAX);
|
2024-08-28 22:23:53 +00:00
|
|
|
case INA2XX_CURRENT:
|
|
|
|
val = clamp_val(val, INT_MIN / 1000, INT_MAX / 1000);
|
|
|
|
/* signed register, result in mA */
|
|
|
|
val = DIV_ROUND_CLOSEST(val * 1000, data->current_lsb_uA);
|
|
|
|
return clamp_val(val, SHRT_MIN, SHRT_MAX);
|
2020-05-05 00:59:45 +00:00
|
|
|
default:
|
|
|
|
/* programmer goofed */
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina226_alert_limit_read(struct ina2xx_data *data, u32 mask, int reg, long *val)
|
2020-05-05 00:59:45 +00:00
|
|
|
{
|
2024-08-01 21:57:39 +00:00
|
|
|
struct regmap *regmap = data->regmap;
|
2020-05-05 00:59:45 +00:00
|
|
|
int regval;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&data->config_lock);
|
2024-08-01 21:57:39 +00:00
|
|
|
ret = regmap_read(regmap, INA226_MASK_ENABLE, ®val);
|
2020-05-05 00:59:45 +00:00
|
|
|
if (ret)
|
|
|
|
goto abort;
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
if (regval & mask) {
|
2024-08-01 21:57:39 +00:00
|
|
|
ret = regmap_read(regmap, INA226_ALERT_LIMIT, ®val);
|
2020-05-05 00:59:45 +00:00
|
|
|
if (ret)
|
|
|
|
goto abort;
|
2024-07-25 05:41:16 +00:00
|
|
|
*val = ina2xx_get_value(data, reg, regval);
|
|
|
|
} else {
|
|
|
|
*val = 0;
|
2020-05-05 00:59:45 +00:00
|
|
|
}
|
|
|
|
abort:
|
|
|
|
mutex_unlock(&data->config_lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2024-08-28 22:18:51 +00:00
|
|
|
static int ina226_alert_limit_write(struct ina2xx_data *data, u32 mask, int reg, long val)
|
2020-05-05 00:59:45 +00:00
|
|
|
{
|
2024-08-01 21:57:39 +00:00
|
|
|
struct regmap *regmap = data->regmap;
|
2020-05-05 00:59:45 +00:00
|
|
|
int ret;
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
if (val < 0)
|
|
|
|
return -EINVAL;
|
2020-05-05 00:59:45 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear all alerts first to avoid accidentally triggering ALERT pin
|
|
|
|
* due to register write sequence. Then, only enable the alert
|
|
|
|
* if the value is non-zero.
|
|
|
|
*/
|
|
|
|
mutex_lock(&data->config_lock);
|
2024-08-01 21:57:39 +00:00
|
|
|
ret = regmap_update_bits(regmap, INA226_MASK_ENABLE,
|
2020-05-05 00:59:45 +00:00
|
|
|
INA226_ALERT_CONFIG_MASK, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
goto abort;
|
|
|
|
|
2024-08-01 21:57:39 +00:00
|
|
|
ret = regmap_write(regmap, INA226_ALERT_LIMIT,
|
2024-08-28 22:18:51 +00:00
|
|
|
ina226_alert_to_reg(data, reg, val));
|
2020-05-05 00:59:45 +00:00
|
|
|
if (ret < 0)
|
|
|
|
goto abort;
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
if (val)
|
2024-08-01 21:57:39 +00:00
|
|
|
ret = regmap_update_bits(regmap, INA226_MASK_ENABLE,
|
2024-07-25 05:41:16 +00:00
|
|
|
INA226_ALERT_CONFIG_MASK, mask);
|
2020-05-05 00:59:45 +00:00
|
|
|
abort:
|
|
|
|
mutex_unlock(&data->config_lock);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina2xx_chip_read(struct device *dev, u32 attr, long *val)
|
2020-05-05 00:59:45 +00:00
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
2024-07-25 05:41:16 +00:00
|
|
|
u32 regval;
|
2020-05-05 00:59:45 +00:00
|
|
|
int ret;
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
switch (attr) {
|
|
|
|
case hwmon_chip_update_interval:
|
|
|
|
ret = regmap_read(data->regmap, INA2XX_CONFIG, ®val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
*val = ina226_reg_to_interval(regval);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ina226_alert_read(struct regmap *regmap, u32 mask, long *val)
|
|
|
|
{
|
|
|
|
unsigned int regval;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = regmap_read_bypassed(regmap, INA226_MASK_ENABLE, ®val);
|
2020-05-05 00:59:45 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
*val = (regval & mask) && (regval & INA226_ALERT_FUNCTION_FLAG);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ina2xx_in_read(struct device *dev, u32 attr, int channel, long *val)
|
|
|
|
{
|
|
|
|
int voltage_reg = channel ? INA2XX_BUS_VOLTAGE : INA2XX_SHUNT_VOLTAGE;
|
|
|
|
u32 under_voltage_mask = channel ? INA226_BUS_UNDER_VOLTAGE_MASK
|
|
|
|
: INA226_SHUNT_UNDER_VOLTAGE_MASK;
|
|
|
|
u32 over_voltage_mask = channel ? INA226_BUS_OVER_VOLTAGE_MASK
|
|
|
|
: INA226_SHUNT_OVER_VOLTAGE_MASK;
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
struct regmap *regmap = data->regmap;
|
|
|
|
unsigned int regval;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_in_input:
|
|
|
|
ret = regmap_read(regmap, voltage_reg, ®val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*val = ina2xx_get_value(data, voltage_reg, regval);
|
|
|
|
break;
|
|
|
|
case hwmon_in_lcrit:
|
|
|
|
return ina226_alert_limit_read(data, under_voltage_mask,
|
|
|
|
voltage_reg, val);
|
|
|
|
case hwmon_in_crit:
|
|
|
|
return ina226_alert_limit_read(data, over_voltage_mask,
|
|
|
|
voltage_reg, val);
|
|
|
|
case hwmon_in_lcrit_alarm:
|
|
|
|
return ina226_alert_read(regmap, under_voltage_mask, val);
|
|
|
|
case hwmon_in_crit_alarm:
|
|
|
|
return ina226_alert_read(regmap, over_voltage_mask, val);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-11-06 15:05:46 +00:00
|
|
|
/*
|
|
|
|
* Configuring the READ_EIN (bit 10) of the ACCUM_CONFIG register to 1
|
|
|
|
* can clear accumulator and sample_count after reading the EIN register.
|
|
|
|
* This way, the average power between the last read and the current
|
|
|
|
* read can be obtained. By combining with accurate time data from
|
|
|
|
* outside, the energy consumption during that period can be calculated.
|
|
|
|
*/
|
|
|
|
static int sy24655_average_power_read(struct ina2xx_data *data, u8 reg, long *val)
|
|
|
|
{
|
|
|
|
u8 template[6];
|
|
|
|
int ret;
|
|
|
|
long accumulator_24, sample_count;
|
|
|
|
|
|
|
|
/* 48-bit register read */
|
|
|
|
ret = i2c_smbus_read_i2c_block_data(data->client, reg, 6, template);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if (ret != 6)
|
|
|
|
return -EIO;
|
|
|
|
accumulator_24 = ((template[3] << 16) |
|
|
|
|
(template[4] << 8) |
|
|
|
|
template[5]);
|
|
|
|
sample_count = ((template[0] << 16) |
|
|
|
|
(template[1] << 8) |
|
|
|
|
template[2]);
|
|
|
|
if (sample_count <= 0) {
|
|
|
|
*val = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
*val = DIV_ROUND_CLOSEST(accumulator_24, sample_count) * data->power_lsb_uW;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina2xx_power_read(struct device *dev, u32 attr, long *val)
|
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_power_input:
|
|
|
|
return ina2xx_read_init(dev, INA2XX_POWER, val);
|
2024-11-06 15:05:46 +00:00
|
|
|
case hwmon_power_average:
|
|
|
|
return sy24655_average_power_read(data, SY24655_EIN, val);
|
2024-07-25 05:41:16 +00:00
|
|
|
case hwmon_power_crit:
|
|
|
|
return ina226_alert_limit_read(data, INA226_POWER_OVER_LIMIT_MASK,
|
|
|
|
INA2XX_POWER, val);
|
|
|
|
case hwmon_power_crit_alarm:
|
|
|
|
return ina226_alert_read(data->regmap, INA226_POWER_OVER_LIMIT_MASK, val);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ina2xx_curr_read(struct device *dev, u32 attr, long *val)
|
|
|
|
{
|
2024-08-28 22:23:53 +00:00
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
struct regmap *regmap = data->regmap;
|
2024-08-29 00:21:41 +00:00
|
|
|
unsigned int regval;
|
|
|
|
int ret;
|
2024-08-28 22:23:53 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* While the chips supported by this driver do not directly support
|
|
|
|
* current limits, they do support setting shunt voltage limits.
|
|
|
|
* The shunt voltage divided by the shunt resistor value is the current.
|
|
|
|
* On top of that, calibration values are set such that in the shunt
|
|
|
|
* voltage register and the current register report the same values.
|
|
|
|
* That means we can report and configure current limits based on shunt
|
|
|
|
* voltage limits.
|
|
|
|
*/
|
2024-07-25 05:41:16 +00:00
|
|
|
switch (attr) {
|
|
|
|
case hwmon_curr_input:
|
2024-08-29 00:21:41 +00:00
|
|
|
/*
|
|
|
|
* Since the shunt voltage and the current register report the
|
|
|
|
* same values when the chip is calibrated, we can calculate
|
|
|
|
* the current directly from the shunt voltage without relying
|
|
|
|
* on chip calibration.
|
|
|
|
*/
|
|
|
|
ret = regmap_read(regmap, INA2XX_SHUNT_VOLTAGE, ®val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*val = ina2xx_get_value(data, INA2XX_CURRENT, regval);
|
|
|
|
return 0;
|
2024-08-28 22:23:53 +00:00
|
|
|
case hwmon_curr_lcrit:
|
|
|
|
return ina226_alert_limit_read(data, INA226_SHUNT_UNDER_VOLTAGE_MASK,
|
|
|
|
INA2XX_CURRENT, val);
|
|
|
|
case hwmon_curr_crit:
|
|
|
|
return ina226_alert_limit_read(data, INA226_SHUNT_OVER_VOLTAGE_MASK,
|
|
|
|
INA2XX_CURRENT, val);
|
|
|
|
case hwmon_curr_lcrit_alarm:
|
|
|
|
return ina226_alert_read(regmap, INA226_SHUNT_UNDER_VOLTAGE_MASK, val);
|
|
|
|
case hwmon_curr_crit_alarm:
|
|
|
|
return ina226_alert_read(regmap, INA226_SHUNT_OVER_VOLTAGE_MASK, val);
|
2024-07-25 05:41:16 +00:00
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
hwmon: (ina2xx) Re-initialize chip using regmap functions
If it is necessary to re-initialize the chip, for example because
it has been power cycled, use regmap functions to update register
contents. This ensures that all registers, including the configuration
register and alert registers, are updated to previously configured
values without having to locally cache everything.
For this to work, volatile registers have to be marked as volatile.
Also, the cache needs to be bypassed when reading the calibration
and mask_enable registers. While the calibration register is not
volatile, it will be reset to 0 if the chip has been power cycled.
Most of the bits in the mask_enable register are configuration bits,
except for bit 4 which reports if an alert has been observed.
Both registers need to be marked as non-volatile to be updated
after a power cycle, but it is necessary to bypass the cache when
reading them to detect if the chip has been power cycled and to
read the alert status.
The chip does not support register auto-increments. It is therefore
necessary to configure regmap to use single register read/write
operations. Otherwise regmap tries to write all registers in a single
operation when synchronizing register contents with the hardware,
and the synchronization fails.
Another necessary change is to declare ina226_alert_to_reg() as u16.
So far it returned an s16 which is sign extended to a large negative
value which is then sent to regmap as unsigned int, causing an -EINVAL
error return.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-23 23:04:29 +00:00
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina2xx_read(struct device *dev, enum hwmon_sensor_types type,
|
|
|
|
u32 attr, int channel, long *val)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case hwmon_chip:
|
|
|
|
return ina2xx_chip_read(dev, attr, val);
|
|
|
|
case hwmon_in:
|
|
|
|
return ina2xx_in_read(dev, attr, channel, val);
|
|
|
|
case hwmon_power:
|
|
|
|
return ina2xx_power_read(dev, attr, val);
|
|
|
|
case hwmon_curr:
|
|
|
|
return ina2xx_curr_read(dev, attr, val);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
2020-05-05 00:59:45 +00:00
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina2xx_chip_write(struct device *dev, u32 attr, long val)
|
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_chip_update_interval:
|
|
|
|
return regmap_update_bits(data->regmap, INA2XX_CONFIG,
|
|
|
|
INA226_AVG_RD_MASK,
|
|
|
|
ina226_interval_to_reg(val));
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ina2xx_in_write(struct device *dev, u32 attr, int channel, long val)
|
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_in_lcrit:
|
|
|
|
return ina226_alert_limit_write(data,
|
|
|
|
channel ? INA226_BUS_UNDER_VOLTAGE_MASK : INA226_SHUNT_UNDER_VOLTAGE_MASK,
|
2024-08-28 22:18:51 +00:00
|
|
|
channel ? INA2XX_BUS_VOLTAGE : INA2XX_SHUNT_VOLTAGE,
|
2024-07-25 05:41:16 +00:00
|
|
|
val);
|
|
|
|
case hwmon_in_crit:
|
|
|
|
return ina226_alert_limit_write(data,
|
|
|
|
channel ? INA226_BUS_OVER_VOLTAGE_MASK : INA226_SHUNT_OVER_VOLTAGE_MASK,
|
2024-08-28 22:18:51 +00:00
|
|
|
channel ? INA2XX_BUS_VOLTAGE : INA2XX_SHUNT_VOLTAGE,
|
2024-07-25 05:41:16 +00:00
|
|
|
val);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ina2xx_power_write(struct device *dev, u32 attr, long val)
|
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_power_crit:
|
2024-08-28 22:18:51 +00:00
|
|
|
return ina226_alert_limit_write(data, INA226_POWER_OVER_LIMIT_MASK,
|
|
|
|
INA2XX_POWER, val);
|
2024-07-25 05:41:16 +00:00
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-08-28 22:23:53 +00:00
|
|
|
static int ina2xx_curr_write(struct device *dev, u32 attr, long val)
|
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_curr_lcrit:
|
|
|
|
return ina226_alert_limit_write(data, INA226_SHUNT_UNDER_VOLTAGE_MASK,
|
|
|
|
INA2XX_CURRENT, val);
|
|
|
|
case hwmon_curr_crit:
|
|
|
|
return ina226_alert_limit_write(data, INA226_SHUNT_OVER_VOLTAGE_MASK,
|
|
|
|
INA2XX_CURRENT, val);
|
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static int ina2xx_write(struct device *dev, enum hwmon_sensor_types type,
|
|
|
|
u32 attr, int channel, long val)
|
|
|
|
{
|
|
|
|
switch (type) {
|
|
|
|
case hwmon_chip:
|
|
|
|
return ina2xx_chip_write(dev, attr, val);
|
|
|
|
case hwmon_in:
|
|
|
|
return ina2xx_in_write(dev, attr, channel, val);
|
|
|
|
case hwmon_power:
|
|
|
|
return ina2xx_power_write(dev, attr, val);
|
2024-08-28 22:23:53 +00:00
|
|
|
case hwmon_curr:
|
|
|
|
return ina2xx_curr_write(dev, attr, val);
|
2024-07-25 05:41:16 +00:00
|
|
|
default:
|
|
|
|
return -EOPNOTSUPP;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static umode_t ina2xx_is_visible(const void *_data, enum hwmon_sensor_types type,
|
|
|
|
u32 attr, int channel)
|
|
|
|
{
|
|
|
|
const struct ina2xx_data *data = _data;
|
2024-08-27 19:57:10 +00:00
|
|
|
bool has_alerts = data->config->has_alerts;
|
2024-11-06 15:05:46 +00:00
|
|
|
bool has_power_average = data->config->has_power_average;
|
2024-07-25 05:41:16 +00:00
|
|
|
enum ina2xx_ids chip = data->chip;
|
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case hwmon_in:
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_in_input:
|
|
|
|
return 0444;
|
|
|
|
case hwmon_in_lcrit:
|
|
|
|
case hwmon_in_crit:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-07-25 05:41:16 +00:00
|
|
|
return 0644;
|
|
|
|
break;
|
|
|
|
case hwmon_in_lcrit_alarm:
|
|
|
|
case hwmon_in_crit_alarm:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-07-25 05:41:16 +00:00
|
|
|
return 0444;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case hwmon_curr:
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_curr_input:
|
|
|
|
return 0444;
|
2024-08-28 22:23:53 +00:00
|
|
|
case hwmon_curr_lcrit:
|
|
|
|
case hwmon_curr_crit:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-08-28 22:23:53 +00:00
|
|
|
return 0644;
|
|
|
|
break;
|
|
|
|
case hwmon_curr_lcrit_alarm:
|
|
|
|
case hwmon_curr_crit_alarm:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-08-28 22:23:53 +00:00
|
|
|
return 0444;
|
|
|
|
break;
|
2024-07-25 05:41:16 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case hwmon_power:
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_power_input:
|
|
|
|
return 0444;
|
|
|
|
case hwmon_power_crit:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-07-25 05:41:16 +00:00
|
|
|
return 0644;
|
|
|
|
break;
|
|
|
|
case hwmon_power_crit_alarm:
|
2024-08-27 19:57:10 +00:00
|
|
|
if (has_alerts)
|
2024-07-25 05:41:16 +00:00
|
|
|
return 0444;
|
|
|
|
break;
|
2024-11-06 15:05:46 +00:00
|
|
|
case hwmon_power_average:
|
|
|
|
if (has_power_average)
|
|
|
|
return 0444;
|
|
|
|
break;
|
2024-07-25 05:41:16 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case hwmon_chip:
|
|
|
|
switch (attr) {
|
|
|
|
case hwmon_chip_update_interval:
|
2024-08-27 17:23:10 +00:00
|
|
|
if (chip == ina226 || chip == ina260)
|
2024-07-25 05:41:16 +00:00
|
|
|
return 0644;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct hwmon_channel_info * const ina2xx_info[] = {
|
|
|
|
HWMON_CHANNEL_INFO(chip,
|
|
|
|
HWMON_C_UPDATE_INTERVAL),
|
|
|
|
HWMON_CHANNEL_INFO(in,
|
|
|
|
HWMON_I_INPUT | HWMON_I_CRIT | HWMON_I_CRIT_ALARM |
|
|
|
|
HWMON_I_LCRIT | HWMON_I_LCRIT_ALARM,
|
|
|
|
HWMON_I_INPUT | HWMON_I_CRIT | HWMON_I_CRIT_ALARM |
|
|
|
|
HWMON_I_LCRIT | HWMON_I_LCRIT_ALARM
|
|
|
|
),
|
2024-08-28 22:23:53 +00:00
|
|
|
HWMON_CHANNEL_INFO(curr, HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM |
|
|
|
|
HWMON_C_LCRIT | HWMON_C_LCRIT_ALARM),
|
2024-07-25 05:41:16 +00:00
|
|
|
HWMON_CHANNEL_INFO(power,
|
2024-11-06 15:05:46 +00:00
|
|
|
HWMON_P_INPUT | HWMON_P_CRIT | HWMON_P_CRIT_ALARM |
|
|
|
|
HWMON_P_AVERAGE),
|
2024-07-25 05:41:16 +00:00
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct hwmon_ops ina2xx_hwmon_ops = {
|
|
|
|
.is_visible = ina2xx_is_visible,
|
|
|
|
.read = ina2xx_read,
|
|
|
|
.write = ina2xx_write,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct hwmon_chip_info ina2xx_chip_info = {
|
|
|
|
.ops = &ina2xx_hwmon_ops,
|
|
|
|
.info = ina2xx_info,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* shunt resistance */
|
|
|
|
|
2017-11-22 15:32:15 +00:00
|
|
|
/*
|
|
|
|
* In order to keep calibration register value fixed, the product
|
|
|
|
* of current_lsb and shunt_resistor should also be fixed and equal
|
|
|
|
* to shunt_voltage_lsb = 1 / shunt_div multiplied by 10^9 in order
|
|
|
|
* to keep the scale.
|
|
|
|
*/
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
static int ina2xx_set_shunt(struct ina2xx_data *data, unsigned long val)
|
2017-11-22 15:32:15 +00:00
|
|
|
{
|
|
|
|
unsigned int dividend = DIV_ROUND_CLOSEST(1000000000,
|
|
|
|
data->config->shunt_div);
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
if (!val || val > dividend)
|
2017-11-22 15:32:15 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
data->rshunt = val;
|
|
|
|
data->current_lsb_uA = DIV_ROUND_CLOSEST(dividend, val);
|
|
|
|
data->power_lsb_uW = data->config->power_lsb_factor *
|
|
|
|
data->current_lsb_uA;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static ssize_t shunt_resistor_show(struct device *dev,
|
|
|
|
struct device_attribute *da, char *buf)
|
2018-08-14 07:09:37 +00:00
|
|
|
{
|
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
|
|
|
|
2021-03-16 11:00:57 +00:00
|
|
|
return sysfs_emit(buf, "%li\n", data->rshunt);
|
2018-08-14 07:09:37 +00:00
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static ssize_t shunt_resistor_store(struct device *dev,
|
|
|
|
struct device_attribute *da,
|
|
|
|
const char *buf, size_t count)
|
2015-01-05 14:20:55 +00:00
|
|
|
{
|
2024-07-25 05:41:16 +00:00
|
|
|
struct ina2xx_data *data = dev_get_drvdata(dev);
|
2015-01-05 14:20:55 +00:00
|
|
|
unsigned long val;
|
|
|
|
int status;
|
|
|
|
|
|
|
|
status = kstrtoul(buf, 10, &val);
|
|
|
|
if (status < 0)
|
|
|
|
return status;
|
|
|
|
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
mutex_lock(&data->config_lock);
|
2017-11-22 15:32:15 +00:00
|
|
|
status = ina2xx_set_shunt(data, val);
|
hwmon: (ina2xx) Fix various overflow issues
Module tests show various overflow problems when writing limits
and other attributes.
in0_crit: Suspected overflow: [max=82, read 0, written 2147483648]
in0_lcrit: Suspected overflow: [max=82, read 0, written 2147483648]
in1_crit: Suspected overflow: [max=40959, read 0, written 2147483647]
in1_lcrit: Suspected overflow: [max=40959, read 0, written 2147483647]
power1_crit: Suspected overflow: [max=134218750, read 0, written 2147483648]
update_interval: Suspected overflow: [max=2253, read 2, written 2147483647]
Implement missing clamping on attribute write operations to avoid those
problems.
While at it, check in the probe function if the shunt resistor value
passed from devicetree is valid, and bail out if it isn't. Also limit
mutex use to the code calling ina2xx_set_shunt() since it isn't needed
when called from the probe function.
Reviewed-by: Tzung-Bi Shih <tzungbi@kernel.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-07-24 16:42:16 +00:00
|
|
|
mutex_unlock(&data->config_lock);
|
2015-01-05 14:20:55 +00:00
|
|
|
if (status < 0)
|
|
|
|
return status;
|
|
|
|
return count;
|
|
|
|
}
|
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
static DEVICE_ATTR_RW(shunt_resistor);
|
2015-01-09 16:03:42 +00:00
|
|
|
|
2012-05-12 08:36:38 +00:00
|
|
|
/* pointers to created device attributes */
|
2013-09-02 20:16:19 +00:00
|
|
|
static struct attribute *ina2xx_attrs[] = {
|
2024-07-25 05:41:16 +00:00
|
|
|
&dev_attr_shunt_resistor.attr,
|
2012-05-12 08:36:38 +00:00
|
|
|
NULL,
|
|
|
|
};
|
2024-07-25 05:41:16 +00:00
|
|
|
ATTRIBUTE_GROUPS(ina2xx);
|
2012-05-12 08:36:38 +00:00
|
|
|
|
2024-07-24 16:31:08 +00:00
|
|
|
/*
|
|
|
|
* Initialize chip
|
|
|
|
*/
|
|
|
|
static int ina2xx_init(struct device *dev, struct ina2xx_data *data)
|
|
|
|
{
|
|
|
|
struct regmap *regmap = data->regmap;
|
|
|
|
u32 shunt;
|
|
|
|
int ret;
|
|
|
|
|
2024-08-27 17:23:10 +00:00
|
|
|
if (data->config->has_ishunt)
|
|
|
|
shunt = INA260_RSHUNT;
|
|
|
|
else if (device_property_read_u32(dev, "shunt-resistor", &shunt) < 0)
|
2024-07-24 16:31:08 +00:00
|
|
|
shunt = INA2XX_RSHUNT_DEFAULT;
|
|
|
|
|
|
|
|
ret = ina2xx_set_shunt(data, shunt);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = regmap_write(regmap, INA2XX_CONFIG, data->config->config_default);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2024-08-27 19:57:10 +00:00
|
|
|
if (data->config->has_alerts) {
|
2024-07-24 16:31:08 +00:00
|
|
|
bool active_high = device_property_read_bool(dev, "ti,alert-polarity-active-high");
|
|
|
|
|
2024-07-23 23:17:02 +00:00
|
|
|
regmap_update_bits(regmap, INA226_MASK_ENABLE,
|
|
|
|
INA226_ALERT_LATCH_ENABLE | INA226_ALERT_POLARITY,
|
|
|
|
INA226_ALERT_LATCH_ENABLE |
|
|
|
|
FIELD_PREP(INA226_ALERT_POLARITY, active_high));
|
2024-07-24 16:31:08 +00:00
|
|
|
}
|
2024-11-06 15:05:46 +00:00
|
|
|
if (data->config->has_power_average) {
|
|
|
|
if (data->chip == sy24655) {
|
|
|
|
/*
|
|
|
|
* Initialize the power accumulation method to continuous
|
|
|
|
* mode and clear the EIN register after each read of the
|
|
|
|
* EIN register
|
|
|
|
*/
|
|
|
|
ret = regmap_write(regmap, SY24655_ACCUM_CONFIG,
|
|
|
|
SY24655_ACCUM_CONFIG_DEFAULT);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
}
|
2024-07-24 16:31:08 +00:00
|
|
|
|
2024-08-27 17:23:10 +00:00
|
|
|
if (data->config->has_ishunt)
|
|
|
|
return 0;
|
|
|
|
|
2024-07-24 16:31:08 +00:00
|
|
|
/*
|
|
|
|
* Calibration register is set to the best value, which eliminates
|
|
|
|
* truncation errors on calculating current register in hardware.
|
|
|
|
* According to datasheet (eq. 3) the best values are 2048 for
|
|
|
|
* ina226 and 4096 for ina219. They are hardcoded as calibration_value.
|
|
|
|
*/
|
|
|
|
return regmap_write(regmap, INA2XX_CALIBRATION,
|
|
|
|
data->config->calibration_value);
|
|
|
|
}
|
|
|
|
|
2020-08-13 16:02:22 +00:00
|
|
|
static int ina2xx_probe(struct i2c_client *client)
|
2012-05-12 08:36:38 +00:00
|
|
|
{
|
2013-09-02 20:16:19 +00:00
|
|
|
struct device *dev = &client->dev;
|
|
|
|
struct ina2xx_data *data;
|
|
|
|
struct device *hwmon_dev;
|
2017-02-24 13:13:00 +00:00
|
|
|
enum ina2xx_ids chip;
|
2024-07-25 05:41:16 +00:00
|
|
|
int ret;
|
2017-02-24 13:13:00 +00:00
|
|
|
|
2024-04-03 20:36:13 +00:00
|
|
|
chip = (uintptr_t)i2c_get_match_data(client);
|
2012-05-12 08:36:38 +00:00
|
|
|
|
2013-09-02 20:16:19 +00:00
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
2012-05-12 08:36:38 +00:00
|
|
|
if (!data)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
/* set the device type */
|
2024-11-06 15:05:46 +00:00
|
|
|
data->client = client;
|
2017-02-24 13:13:00 +00:00
|
|
|
data->config = &ina2xx_config[chip];
|
2024-07-24 16:31:08 +00:00
|
|
|
data->chip = chip;
|
2018-01-15 13:58:21 +00:00
|
|
|
mutex_init(&data->config_lock);
|
2015-01-09 16:03:42 +00:00
|
|
|
|
2015-10-28 11:04:53 +00:00
|
|
|
data->regmap = devm_regmap_init_i2c(client, &ina2xx_regmap_config);
|
|
|
|
if (IS_ERR(data->regmap)) {
|
|
|
|
dev_err(dev, "failed to allocate register map\n");
|
|
|
|
return PTR_ERR(data->regmap);
|
|
|
|
}
|
|
|
|
|
2023-04-07 16:05:08 +00:00
|
|
|
ret = devm_regulator_get_enable(dev, "vs");
|
|
|
|
if (ret)
|
|
|
|
return dev_err_probe(dev, ret, "failed to enable vs regulator\n");
|
|
|
|
|
2024-07-24 16:31:08 +00:00
|
|
|
ret = ina2xx_init(dev, data);
|
|
|
|
if (ret < 0)
|
|
|
|
return dev_err_probe(dev, ret, "failed to configure device\n");
|
2012-05-12 08:36:38 +00:00
|
|
|
|
2024-07-25 05:41:16 +00:00
|
|
|
hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
|
|
|
|
data, &ina2xx_chip_info,
|
2024-08-27 17:23:10 +00:00
|
|
|
data->config->has_ishunt ?
|
|
|
|
NULL : ina2xx_groups);
|
2013-09-02 20:16:19 +00:00
|
|
|
if (IS_ERR(hwmon_dev))
|
|
|
|
return PTR_ERR(hwmon_dev);
|
2012-05-12 08:36:38 +00:00
|
|
|
|
2013-09-02 20:16:19 +00:00
|
|
|
dev_info(dev, "power monitor %s (Rshunt = %li uOhm)\n",
|
2018-11-10 00:42:14 +00:00
|
|
|
client->name, data->rshunt);
|
2012-05-12 18:21:01 +00:00
|
|
|
|
2012-05-12 08:36:38 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_device_id ina2xx_id[] = {
|
|
|
|
{ "ina219", ina219 },
|
2012-05-12 18:33:11 +00:00
|
|
|
{ "ina220", ina219 },
|
2012-05-12 08:36:38 +00:00
|
|
|
{ "ina226", ina226 },
|
2012-05-12 18:33:11 +00:00
|
|
|
{ "ina230", ina226 },
|
2015-01-15 01:34:58 +00:00
|
|
|
{ "ina231", ina226 },
|
2024-08-27 17:23:10 +00:00
|
|
|
{ "ina260", ina260 },
|
2024-11-06 15:05:46 +00:00
|
|
|
{ "sy24655", sy24655 },
|
2012-05-12 08:36:38 +00:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, ina2xx_id);
|
|
|
|
|
2019-04-04 15:00:57 +00:00
|
|
|
static const struct of_device_id __maybe_unused ina2xx_of_match[] = {
|
2024-11-06 15:05:46 +00:00
|
|
|
{
|
|
|
|
.compatible = "silergy,sy24655",
|
|
|
|
.data = (void *)sy24655
|
|
|
|
},
|
2017-02-24 13:13:00 +00:00
|
|
|
{
|
|
|
|
.compatible = "ti,ina219",
|
|
|
|
.data = (void *)ina219
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,ina220",
|
|
|
|
.data = (void *)ina219
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,ina226",
|
|
|
|
.data = (void *)ina226
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,ina230",
|
|
|
|
.data = (void *)ina226
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,ina231",
|
|
|
|
.data = (void *)ina226
|
|
|
|
},
|
2024-08-27 17:23:10 +00:00
|
|
|
{
|
|
|
|
.compatible = "ti,ina260",
|
|
|
|
.data = (void *)ina260
|
|
|
|
},
|
2024-11-06 15:05:46 +00:00
|
|
|
{ }
|
2017-02-24 13:13:00 +00:00
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, ina2xx_of_match);
|
|
|
|
|
2012-05-12 08:36:38 +00:00
|
|
|
static struct i2c_driver ina2xx_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "ina2xx",
|
2017-02-24 13:13:00 +00:00
|
|
|
.of_match_table = of_match_ptr(ina2xx_of_match),
|
2012-05-12 08:36:38 +00:00
|
|
|
},
|
2023-05-05 13:17:18 +00:00
|
|
|
.probe = ina2xx_probe,
|
2012-05-12 08:36:38 +00:00
|
|
|
.id_table = ina2xx_id,
|
|
|
|
};
|
|
|
|
|
2012-10-08 12:40:35 +00:00
|
|
|
module_i2c_driver(ina2xx_driver);
|
2012-05-12 08:36:38 +00:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Lothar Felten <l-felten@ti.com>");
|
|
|
|
MODULE_DESCRIPTION("ina2xx driver");
|
|
|
|
MODULE_LICENSE("GPL");
|