2024-01-22 00:19:14 +00:00
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# SPDX-License-Identifier: GPL-2.0
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menu "Accelerated Cryptographic Algorithms for CPU (riscv)"
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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config CRYPTO_AES_RISCV64
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2024-02-13 05:54:42 +00:00
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tristate "Ciphers: AES, modes: ECB, CBC, CTS, CTR, XTS"
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_ALGAPI
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select CRYPTO_LIB_AES
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select CRYPTO_SKCIPHER
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help
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Block cipher: AES cipher algorithms
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2024-02-13 05:54:42 +00:00
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Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XTS
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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Architecture: riscv64 using:
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- Zvkned vector crypto extension
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- Zvbb vector extension (XTS)
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- Zvkb vector crypto extension (CTR)
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- Zvkg vector crypto extension (XTS)
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2024-01-22 00:19:16 +00:00
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config CRYPTO_CHACHA_RISCV64
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tristate "Ciphers: ChaCha"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_SKCIPHER
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select CRYPTO_LIB_CHACHA_GENERIC
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help
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Length-preserving ciphers: ChaCha20 stream cipher algorithm
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Architecture: riscv64 using:
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- Zvkb vector crypto extension
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2024-01-22 00:19:17 +00:00
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config CRYPTO_GHASH_RISCV64
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tristate "Hash functions: GHASH"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_GCM
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help
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GCM GHASH function (NIST SP 800-38D)
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Architecture: riscv64 using:
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- Zvkg vector crypto extension
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2024-01-22 00:19:18 +00:00
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config CRYPTO_SHA256_RISCV64
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tristate "Hash functions: SHA-224 and SHA-256"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_SHA256
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help
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SHA-224 and SHA-256 secure hash algorithm (FIPS 180)
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Architecture: riscv64 using:
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- Zvknha or Zvknhb vector crypto extensions
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- Zvkb vector crypto extension
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2024-01-22 00:19:19 +00:00
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config CRYPTO_SHA512_RISCV64
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tristate "Hash functions: SHA-384 and SHA-512"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_SHA512
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help
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SHA-384 and SHA-512 secure hash algorithm (FIPS 180)
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Architecture: riscv64 using:
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- Zvknhb vector crypto extension
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- Zvkb vector crypto extension
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2024-01-22 00:19:20 +00:00
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config CRYPTO_SM3_RISCV64
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tristate "Hash functions: SM3 (ShangMi 3)"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_HASH
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select CRYPTO_SM3
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help
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SM3 (ShangMi 3) secure hash function (OSCCA GM/T 0004-2012)
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Architecture: riscv64 using:
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- Zvksh vector crypto extension
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- Zvkb vector crypto extension
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2024-01-22 00:19:21 +00:00
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config CRYPTO_SM4_RISCV64
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tristate "Ciphers: SM4 (ShangMi 4)"
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depends on 64BIT && RISCV_ISA_V && TOOLCHAIN_HAS_VECTOR_CRYPTO
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select CRYPTO_ALGAPI
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select CRYPTO_SM4
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help
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SM4 block cipher algorithm (OSCCA GB/T 32907-2016,
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ISO/IEC 18033-3:2010/Amd 1:2021)
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SM4 (GBT.32907-2016) is a cryptographic standard issued by the
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Organization of State Commercial Administration of China (OSCCA)
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as an authorized cryptographic algorithm for use within China.
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Architecture: riscv64 using:
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- Zvksed vector crypto extension
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- Zvkb vector crypto extension
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2024-01-22 00:19:14 +00:00
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endmenu
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