2022-02-04 15:18:31 +00:00
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What: /sys/bus/cxl/flush
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Date: Januarry, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) If userspace manually unbinds a port the kernel schedules
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all descendant memdevs for unbind. Writing '1' to this attribute
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flushes that work.
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2022-07-10 16:56:05 +00:00
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2021-02-17 04:09:52 +00:00
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What: /sys/bus/cxl/devices/memX/firmware_version
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "FW Revision" string as reported by the Identify
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Memory Device Output Payload in the CXL-2.0
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specification.
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2022-07-10 16:56:05 +00:00
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2021-02-17 04:09:52 +00:00
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What: /sys/bus/cxl/devices/memX/ram/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Volatile Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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2022-07-10 16:56:05 +00:00
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2021-02-17 04:09:52 +00:00
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What: /sys/bus/cxl/devices/memX/pmem/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Persistent Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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2021-06-09 16:01:35 +00:00
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2022-07-10 16:56:05 +00:00
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2022-01-31 21:56:11 +00:00
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What: /sys/bus/cxl/devices/memX/serial
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) 64-bit serial number per the PCIe Device Serial Number
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capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
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Memory Device PCIe Capabilities and Extended Capabilities.
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2022-07-10 16:56:05 +00:00
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2022-01-24 00:31:24 +00:00
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What: /sys/bus/cxl/devices/memX/numa_node
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Date: January, 2022
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) If NUMA is enabled and the platform has affinitized the
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host PCI device for this memory device, emit the CPU node
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affinity for this device.
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:01:35 +00:00
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What: /sys/bus/cxl/devices/*/devtype
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL device objects export the devtype attribute which
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mirrors the same value communicated in the DEVTYPE environment
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variable for uevents for devices on the "cxl" bus.
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2021-06-09 16:01:35 +00:00
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2022-07-10 16:56:05 +00:00
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2022-01-24 00:30:41 +00:00
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What: /sys/bus/cxl/devices/*/modalias
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Date: December, 2021
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KernelVersion: v5.18
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL device objects export the modalias attribute which
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mirrors the same value communicated in the MODALIAS environment
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variable for uevents for devices on the "cxl" bus.
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2022-01-24 00:30:41 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:01:35 +00:00
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What: /sys/bus/cxl/devices/portX/uport
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL port objects are enumerated from either a platform
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firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
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port with CXL component registers. The 'uport' symlink connects
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the CXL portX object to the device that published the CXL port
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2021-06-09 16:01:35 +00:00
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capability.
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2021-06-09 16:01:46 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:01:46 +00:00
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What: /sys/bus/cxl/devices/portX/dportY
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL port objects are enumerated from either a platform
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firmware device (ACPI0017 and ACPI0016) or PCIe switch upstream
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port with CXL component registers. The 'dportY' symlink
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identifies one or more downstream ports that the upstream port
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may target in its decode of CXL memory resources. The 'Y'
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integer reflects the hardware port unique-id used in the
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hardware decoder target list.
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2021-06-09 16:43:29 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL decoder objects are enumerated from either a platform
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2021-06-09 16:43:29 +00:00
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firmware description, or a CXL HDM decoder register set in a
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PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
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Capability Structure). The 'X' in decoderX.Y represents the
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cxl_port container of this decoder, and 'Y' represents the
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instance id of a given decoder resource.
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) The 'start' and 'size' attributes together convey the
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physical address base and number of bytes mapped in the
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decoder's decode window. For decoders of devtype
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"cxl_decoder_root" the address range is fixed. For decoders of
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devtype "cxl_decoder_switch" the address is bounded by the
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decode range of the cxl_port ancestor of the decoder's cxl_port,
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and dynamically updates based on the active memory regions in
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that address space.
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2021-06-09 16:43:29 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/locked
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) CXL HDM decoders have the capability to lock the
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configuration until the next device reset. For decoders of
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devtype "cxl_decoder_root" there is no standard facility to
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unlock them. For decoders of devtype "cxl_decoder_switch" a
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secondary bus reset, of the PCIe bridge that provides the bus
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for this decoders uport, unlocks / resets the decoder.
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2021-06-09 16:43:29 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/target_list
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) Display a comma separated list of the current decoder
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target configuration. The list is ordered by the current
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configured interleave order of the decoder's dport instances.
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Each entry in the list is a dport id.
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2021-06-09 16:43:29 +00:00
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) When a CXL decoder is of devtype "cxl_decoder_root", it
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2021-06-09 16:43:29 +00:00
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represents a fixed memory window identified by platform
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firmware. A fixed window may only support a subset of memory
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types. The 'cap_*' attributes indicate whether persistent
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memory, volatile memory, accelerator memory, and / or expander
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memory may be mapped behind this decoder's memory window.
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2022-07-10 16:56:05 +00:00
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2021-06-09 16:43:29 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/target_type
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-06-22 00:23:16 +00:00
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(RO) When a CXL decoder is of devtype "cxl_decoder_switch", it
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can optionally decode either accelerator memory (type-2) or
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expander memory (type-3). The 'target_type' attribute indicates
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the current setting which may dynamically change based on what
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2021-06-09 16:43:29 +00:00
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memory regions are activated in this decode hierarchy.
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2022-07-19 20:52:49 +00:00
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2022-07-10 16:56:05 +00:00
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2022-07-19 20:52:49 +00:00
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What: /sys/bus/cxl/devices/endpointX/CDAT
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Date: July, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) If this sysfs entry is not present no DOE mailbox was
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found to support CDAT data. If it is present and the length of
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the data is 0 reading the CDAT data failed. Otherwise the CDAT
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data is reported.
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2022-05-23 19:15:35 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/mode
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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2022-05-24 01:02:30 +00:00
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(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
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2022-05-23 19:15:35 +00:00
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translates from a host physical address range, to a device local
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address range. Device-local address ranges are further split
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into a 'ram' (volatile memory) range and 'pmem' (persistent
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memory) range. The 'mode' attribute emits one of 'ram', 'pmem',
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'mixed', or 'none'. The 'mixed' indication is for error cases
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when a decoder straddles the volatile/persistent partition
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boundary, and 'none' indicates the decoder is not actively
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decoding, or no DPA allocation policy has been set.
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2022-05-24 01:02:30 +00:00
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'mode' can be written, when the decoder is in the 'disabled'
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state, with either 'ram' or 'pmem' to set the boundaries for the
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next allocation.
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What: /sys/bus/cxl/devices/decoderX.Y/dpa_resource
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) When a CXL decoder is of devtype "cxl_decoder_endpoint",
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and its 'dpa_size' attribute is non-zero, this attribute
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indicates the device physical address (DPA) base address of the
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allocation.
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What: /sys/bus/cxl/devices/decoderX.Y/dpa_size
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) When a CXL decoder is of devtype "cxl_decoder_endpoint" it
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translates from a host physical address range, to a device local
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address range. The range, base address plus length in bytes, of
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DPA allocated to this decoder is conveyed in these 2 attributes.
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Allocations can be mutated as long as the decoder is in the
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disabled state. A write to 'dpa_size' releases the previous DPA
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allocation and then attempts to allocate from the free capacity
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in the device partition referred to by 'decoderX.Y/mode'.
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Allocate and free requests can only be performed on the highest
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instance number disabled decoder with non-zero size. I.e.
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allocations are enforced to occur in increasing 'decoderX.Y/id'
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order and frees are enforced to occur in decreasing
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'decoderX.Y/id' order.
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2022-04-10 22:26:13 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/interleave_ways
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The number of targets across which this decoder's host
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physical address (HPA) memory range is interleaved. The device
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maps every Nth block of HPA (of size ==
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'interleave_granularity') to consecutive DPA addresses. The
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decoder's position in the interleave is determined by the
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device's (endpoint or switch) switch ancestry. For root
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decoders their interleave is specified by platform firmware and
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they only specify a downstream target order for host bridges.
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What: /sys/bus/cxl/devices/decoderX.Y/interleave_granularity
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) The number of consecutive bytes of host physical address
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space this decoder claims at address N before the decode rotates
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to the next target in the interleave at address N +
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interleave_granularity (assuming N is aligned to
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interleave_granularity).
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cxl/region: Add region creation support
CXL 2.0 allows for dynamic provisioning of new memory regions (system
physical address resources like "System RAM" and "Persistent Memory").
Whereas DDR and PMEM resources are conveyed statically at boot, CXL
allows for assembling and instantiating new regions from the available
capacity of CXL memory expanders in the system.
Sysfs with an "echo $region_name > $create_region_attribute" interface
is chosen as the mechanism to initiate the provisioning process. This
was chosen over ioctl() and netlink() to keep the configuration
interface entirely in a pseudo-fs interface, and it was chosen over
configfs since, aside from this one creation event, the interface is
read-mostly. I.e. configfs supports cases where an object is designed to
be provisioned each boot, like an iSCSI storage target, and CXL region
creation is mostly for PMEM regions which are created usually once
per-lifetime of a server instance. This is an improvement over nvdimm
that pre-created "seed" devices that tended to confuse users looking to
determine which devices are active and which are idle.
Recall that the major change that CXL brings over previous persistent
memory architectures is the ability to dynamically define new regions.
Compare that to drivers like 'nfit' where the region configuration is
statically defined by platform firmware.
Regions are created as a child of a root decoder that encompasses an
address space with constraints. When created through sysfs, the root
decoder is explicit. When created from an LSA's region structure a root
decoder will possibly need to be inferred by the driver.
Upon region creation through sysfs, a vacant region is created with a
unique name. Regions have a number of attributes that must be configured
before the region can be bound to the driver where HDM decoder program
is completed.
An example of creating a new region:
- Allocate a new region name:
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
- Create a new region by name:
while
region=$(cat /sys/bus/cxl/devices/decoder0.0/create_pmem_region)
! echo $region > /sys/bus/cxl/devices/decoder0.0/create_pmem_region
do true; done
- Region now exists in sysfs:
stat -t /sys/bus/cxl/devices/decoder0.0/$region
- Delete the region, and name:
echo $region > /sys/bus/cxl/devices/decoder0.0/delete_region
Signed-off-by: Ben Widawsky <bwidawsk@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/165784333909.1758207.794374602146306032.stgit@dwillia2-xfh.jf.intel.com
[djbw: simplify locking, reword changelog]
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-06-08 17:28:34 +00:00
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What: /sys/bus/cxl/devices/decoderX.Y/create_pmem_region
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Write a string in the form 'regionZ' to start the process
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of defining a new persistent memory region (interleave-set)
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within the decode range bounded by root decoder 'decoderX.Y'.
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The value written must match the current value returned from
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reading this attribute. An atomic compare exchange operation is
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done on write to assign the requested id to a region and
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allocate the region-id for the next creation attempt. EBUSY is
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returned if the region name written does not match the current
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cached value.
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What: /sys/bus/cxl/devices/decoderX.Y/delete_region
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(WO) Write a string in the form 'regionZ' to delete that region,
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provided it is currently idle / not bound to a driver.
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2021-05-27 20:30:41 +00:00
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What: /sys/bus/cxl/devices/regionZ/uuid
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Date: May, 2022
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KernelVersion: v5.20
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RW) Write a unique identifier for the region. This field must
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be set for persistent regions and it must not conflict with the
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UUID of another region.
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