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Pin control fixes for the v6.11 series:

Browse Source 
- One Intel patch that I mistakedly merged into for-next
   despite it belongs in fixes: add Arrow Lake-H/U ACPI
   ID so this Arrow Lake chip probes.
 
 - One fix making the CY895x0 reg cache work, which is
   good because it makes the device work too.
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Merge tag 'pinctrl-v6.11-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - One Intel patch that I mistakenly merged into for-next despite it
   belonging in fixes: add Arrow Lake-H/U ACPI ID so this Arrow Lake
   chip probes.

 - One fix making the CY895x0 reg cache work, which is good because it
   makes the device work too.

* tag 'pinctrl-v6.11-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: pinctrl-cy8c95x0: Fix regcache
  pinctrl: meteorlake: Add Arrow Lake-H/U ACPI ID
This commit is contained in:
Linus Torvalds 2024-09-14 16:58:02 +02:00
commit 0babf68378
2 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/pinctrl/intel/pinctrl-meteorlake.c
View File

@ -584,6 +584,7 @@ static const struct intel_pinctrl_soc_data mtls_soc_data = {
};
static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
{ "INTC105E", (kernel_ulong_t)&mtlp_soc_data },
{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
{ "INTC1082", (kernel_ulong_t)&mtls_soc_data },
{ }

14
drivers/pinctrl/pinctrl-cy8c95x0.c
View File

@ -62,11 +62,11 @@
#define MAX_BANK 8
#define BANK_SZ 8
#define MAX_LINE (MAX_BANK * BANK_SZ)
#define MUXED_STRIDE (CY8C95X0_DRV_HIZ - CY8C95X0_INTMASK)
#define MUXED_STRIDE 16
#define CY8C95X0_GPIO_MASK GENMASK(7, 0)
#define CY8C95X0_VIRTUAL (CY8C95X0_COMMAND + 1)
#define CY8C95X0_VIRTUAL 0x40
#define CY8C95X0_MUX_REGMAP_TO_OFFSET(x, p) \
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_INTMASK + (p) * MUXED_STRIDE)
(CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
static const struct i2c_device_id cy8c95x0_id[] = {
{ "cy8c9520", 20, },
@ -329,7 +329,11 @@ static int cypress_get_pin_mask(struct cy8c95x0_pinctrl *chip, unsigned int pin)
static bool cy8c95x0_readable_register(struct device *dev, unsigned int reg)
{
if (reg >= CY8C95X0_VIRTUAL)
/*
* Only 12 registers are present per port (see Table 6 in the
* datasheet).
*/
if (reg >= CY8C95X0_VIRTUAL && (reg % MUXED_STRIDE) < 12)
return true;
switch (reg) {
@ -444,7 +448,7 @@ static const struct regmap_range_cfg cy8c95x0_ranges[] = {
.selector_reg = CY8C95X0_PORTSEL,
.selector_mask = 0x07,
.selector_shift = 0x0,
.window_start = CY8C95X0_INTMASK,
.window_start = CY8C95X0_PORTSEL,
.window_len = MUXED_STRIDE,
}
};