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dmaengine: dw: Initialize max_sg_burst capability
Multi-block support provides a way to map the kernel-specific SG-table so the DW DMA device would handle it as a whole instead of handling the SG-list items or so called LLP block items one by one. So if true LLP list isn't supported by the DW DMA engine, then soft-LLP mode will be utilized to load and execute each LLP-block one by one. The soft-LLP mode of the DMA transactions execution might not work well for some DMA consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's initialize the max_sg_burst DMA channels capability based on the nollp flag state. If it's true, no hardware accelerated LLP is available and max_sg_burst should be set with 1, which means that the DMA engine can handle only a single SG list entry at a time. If noLLP is set to false, then hardware accelerated LLP is supported and the DMA engine can handle infinite number of SG entries in a single DMA transaction. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200723005848.31907-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
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struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
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caps->max_burst = dwc->max_burst;
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/*
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* It might be crucial for some devices to have the hardware
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* accelerated multi-block transfers supported, aka LLPs in DW DMAC
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* notation. So if LLPs are supported then max_sg_burst is set to
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* zero which means unlimited number of SG entries can be handled in a
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* single DMA transaction, otherwise it's just one SG entry.
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*/
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if (dwc->nollp)
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caps->max_sg_burst = 1;
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else
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caps->max_sg_burst = 0;
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}
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int do_dma_probe(struct dw_dma_chip *chip)
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