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arm64: Get rid of ARM64_HAS_NO_HW_PREFETCH
Back in 2016, it was argued that implementations lacking a HW prefetcher could be helped by sprinkling a number of PRFM instructions in strategic locations. In 2023, the one platform that presumably needed this hack is no longer in active use (let alone maintained), and an quick experiment shows dropping this hack only leads to a 0.4% drop on a full kernel compilation (tested on a MT30-GS0 48 CPU system). Given that this is pretty much in the noise department and that it may give odd ideas to other implementers, drop the hack for good. Suggested-by: Will Deacon <will@kernel.org> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20231122133754.1240687-1-maz@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
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@ -1584,16 +1584,6 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry,
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return has_sre;
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}
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static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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u32 midr = read_cpuid_id();
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/* Cavium ThunderX pass 1.x and 2.x */
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return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
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}
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static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
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int scope)
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{
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@ -2321,12 +2311,6 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP)
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},
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#endif /* CONFIG_ARM64_LSE_ATOMICS */
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{
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.desc = "Software prefetching using PRFM",
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.capability = ARM64_HAS_NO_HW_PREFETCH,
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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.matches = has_no_hw_prefetch,
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},
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{
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.desc = "Virtualization Host Extensions",
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.capability = ARM64_HAS_VIRT_HOST_EXTN,
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@ -18,13 +18,6 @@
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* x1 - src
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*/
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SYM_FUNC_START(__pi_copy_page)
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alternative_if ARM64_HAS_NO_HW_PREFETCH
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// Prefetch three cache lines ahead.
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prfm pldl1strm, [x1, #128]
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prfm pldl1strm, [x1, #256]
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prfm pldl1strm, [x1, #384]
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alternative_else_nop_endif
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ldp x2, x3, [x1]
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ldp x4, x5, [x1, #16]
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ldp x6, x7, [x1, #32]
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@ -39,10 +32,6 @@ alternative_else_nop_endif
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1:
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tst x0, #(PAGE_SIZE - 1)
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alternative_if ARM64_HAS_NO_HW_PREFETCH
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prfm pldl1strm, [x1, #384]
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alternative_else_nop_endif
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stnp x2, x3, [x0, #-256]
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ldp x2, x3, [x1]
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stnp x4, x5, [x0, #16 - 256]
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@ -40,7 +40,6 @@ HAS_LDAPR
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HAS_LSE_ATOMICS
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HAS_MOPS
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HAS_NESTED_VIRT
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HAS_NO_HW_PREFETCH
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HAS_PAN
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HAS_S1PIE
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HAS_RAS_EXTN
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