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net: sxgbe: add TSO support for Samsung sxgbe
Enable TSO during initialization for each DMA channels Signed-off-by: Vipul Pandya <vipul.pandya@samsung.com> Neatening-by: Joe Perches <joe@perches.com> Signed-off-by: Byungho An <bh74.an@samsung.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -371,6 +371,7 @@ struct sxgbe_tx_queue {
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u32 tx_coal_frames;
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u32 tx_coal_timer;
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int hwts_tx_en;
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u16 prev_mss;
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u8 queue_no;
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};
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@ -133,7 +133,7 @@ static int sxgbe_tx_ctxt_desc_get_owner(struct sxgbe_tx_ctxt_desc *p)
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}
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/* Set TX mss in TX context Descriptor */
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static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, int mss)
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static void sxgbe_tx_ctxt_desc_set_mss(struct sxgbe_tx_ctxt_desc *p, u16 mss)
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{
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p->maxseg_size = mss;
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}
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@ -168,7 +168,7 @@ struct sxgbe_desc_ops {
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/* Invoked by the xmit function to prepare the tx descriptor */
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void (*tx_desc_enable_tse)(struct sxgbe_tx_norm_desc *p, u8 is_tse,
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u32 total_hdr_len, u32 payload_len,
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u32 total_hdr_len, u32 tcp_hdr_len,
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u32 tcp_payload_len);
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/* Assign buffer lengths for descriptor */
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@ -217,7 +217,7 @@ struct sxgbe_desc_ops {
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int (*get_tx_ctxt_owner)(struct sxgbe_tx_ctxt_desc *p);
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/* Set TX mss */
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void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, int mss);
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void (*tx_ctxt_desc_set_mss)(struct sxgbe_tx_ctxt_desc *p, u16 mss);
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/* Set TX mss */
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int (*tx_ctxt_desc_get_mss)(struct sxgbe_tx_ctxt_desc *p);
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@ -349,6 +349,15 @@ static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt)
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}
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}
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static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num)
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{
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u32 ctrl;
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ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
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ctrl |= SXGBE_DMA_CHA_TXCTL_TSE_ENABLE;
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writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num));
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}
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static const struct sxgbe_dma_ops sxgbe_dma_ops = {
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.init = sxgbe_dma_init,
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.cha_init = sxgbe_dma_channel_init,
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@ -364,6 +373,7 @@ static const struct sxgbe_dma_ops sxgbe_dma_ops = {
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.tx_dma_int_status = sxgbe_tx_dma_int_status,
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.rx_dma_int_status = sxgbe_rx_dma_int_status,
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.rx_watchdog = sxgbe_dma_rx_watchdog,
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.enable_tso = sxgbe_enable_tso,
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};
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const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void)
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@ -41,6 +41,8 @@ struct sxgbe_dma_ops {
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struct sxgbe_extra_stats *x);
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/* Program the HW RX Watchdog */
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void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt);
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/* Enable TSO for each DMA channel */
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void (*enable_tso)(void __iomem *ioaddr, u8 chan_num);
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};
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const struct sxgbe_dma_ops *sxgbe_get_dma_ops(void);
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@ -1219,6 +1219,28 @@ static int sxgbe_release(struct net_device *dev)
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return 0;
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}
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/* Prepare first Tx descriptor for doing TSO operation */
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void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
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struct sxgbe_tx_norm_desc *first_desc,
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struct sk_buff *skb)
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{
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unsigned int total_hdr_len, tcp_hdr_len;
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/* Write first Tx descriptor with appropriate value */
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tcp_hdr_len = tcp_hdrlen(skb);
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total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
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first_desc->tdes01 = dma_map_single(priv->device, skb->data,
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total_hdr_len, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->device, first_desc->tdes01))
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pr_err("%s: TX dma mapping failed!!\n", __func__);
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first_desc->tdes23.tx_rd_des23.first_desc = 1;
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priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
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tcp_hdr_len,
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skb->len - total_hdr_len);
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}
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/**
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* sxgbe_xmit: Tx entry point of the driver
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* @skb : the socket buffer
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@ -1236,13 +1258,24 @@ static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
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unsigned int tx_rsize = priv->dma_tx_size;
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struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
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struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
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struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
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int nr_frags = skb_shinfo(skb)->nr_frags;
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int no_pagedlen = skb_headlen(skb);
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int is_jumbo = 0;
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u16 cur_mss = skb_shinfo(skb)->gso_size;
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u32 ctxt_desc_req = 0;
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/* get the TX queue handle */
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dev_txq = netdev_get_tx_queue(dev, txq_index);
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if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
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ctxt_desc_req = 1;
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if (unlikely(vlan_tx_tag_present(skb) ||
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((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
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tqueue->hwts_tx_en)))
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ctxt_desc_req = 1;
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/* get the spinlock */
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spin_lock(&tqueue->tx_lock);
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@ -1264,18 +1297,43 @@ static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
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tx_desc = tqueue->dma_tx + entry;
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first_desc = tx_desc;
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if (ctxt_desc_req)
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ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
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/* save the skb address */
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tqueue->tx_skbuff[entry] = skb;
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if (!is_jumbo) {
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tx_desc->tdes01 = dma_map_single(priv->device, skb->data,
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no_pagedlen, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->device, tx_desc->tdes01))
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pr_err("%s: TX dma mapping failed!!\n", __func__);
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if (likely(skb_is_gso(skb))) {
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/* TSO support */
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if (unlikely(tqueue->prev_mss != cur_mss)) {
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priv->hw->desc->tx_ctxt_desc_set_mss(
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ctxt_desc, cur_mss);
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priv->hw->desc->tx_ctxt_desc_set_tcmssv(
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ctxt_desc);
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priv->hw->desc->tx_ctxt_desc_reset_ostc(
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ctxt_desc);
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priv->hw->desc->tx_ctxt_desc_set_ctxt(
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ctxt_desc);
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priv->hw->desc->tx_ctxt_desc_set_owner(
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ctxt_desc);
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priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
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no_pagedlen, 0);
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entry = (++tqueue->cur_tx) % tx_rsize;
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first_desc = tqueue->dma_tx + entry;
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tqueue->prev_mss = cur_mss;
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}
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sxgbe_tso_prepare(priv, first_desc, skb);
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} else {
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tx_desc->tdes01 = dma_map_single(priv->device,
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skb->data, no_pagedlen, DMA_TO_DEVICE);
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if (dma_mapping_error(priv->device, tx_desc->tdes01))
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netdev_err(dev, "%s: TX dma mapping failed!!\n",
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__func__);
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priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
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no_pagedlen, 0);
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}
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}
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for (frag_num = 0; frag_num < nr_frags; frag_num++) {
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@ -2005,6 +2063,7 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
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struct sxgbe_priv_data *priv;
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struct net_device *ndev;
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int ret;
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u8 queue_num;
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ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
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SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
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@ -2038,7 +2097,9 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
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ndev->netdev_ops = &sxgbe_netdev_ops;
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ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
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ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
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NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
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NETIF_F_GRO;
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ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
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ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
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@ -2047,6 +2108,13 @@ struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
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priv->msg_enable = netif_msg_init(debug, default_msg_level);
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/* Enable TCP segmentation offload for all DMA channels */
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if (priv->hw_cap.tcpseg_offload) {
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SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
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priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
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}
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}
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/* Rx Watchdog is available, enable depend on platform data */
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if (!priv->plat->riwt_off) {
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priv->use_riwt = 1;
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