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tools/power turbostat: Enhance platform divergence description

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In various generations, platforms often share a majority of features,
diverging only in a few specific aspects. The current approach of using
hardcoded values in 'platform_features' structure fails to effectively
represent these divergences.

To improve the description of platform divergence:
1. Each newly introduced 'platform_features' structure must have a base,
   typically derived from the previous generation.
2. Platform feature values should be inherited from the base structure
   rather than being hardcoded.
This approach ensures a more accurate and maintainable representation of
platform-specific features across different generations.

Converts `adl_features` and `lnl_features` to follow this new scheme.

No functional change.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Zhang Rui 2024-11-14 15:59:42 +08:00 committed by Len Brown
parent d39d586ee4
commit 1958f4e168
1 changed files with 30 additions and 28 deletions
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58
tools/power/x86/turbostat/turbostat.c
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@ -735,38 +735,40 @@ static const struct platform_features cnl_features = {
.enable_tsc_tweak = 1,
};
/* Copied from cnl_features, with PC7/PC9 removed */
static const struct platform_features adl_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
.has_nhm_msrs = 1,
.has_config_tdp = 1,
.bclk_freq = BCLK_100MHZ,
.supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10,
.cst_limit = CST_LIMIT_HSW,
.has_irtl_msrs = 1,
.has_msr_core_c1_res = 1,
.has_ext_cst_msrs = 1,
.trl_msrs = TRL_BASE,
.tcc_offset_bits = 6,
.rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
.enable_tsc_tweak = 1,
.has_msr_misc_feature_control = cnl_features.has_msr_misc_feature_control,
.has_msr_misc_pwr_mgmt = cnl_features.has_msr_misc_pwr_mgmt,
.has_nhm_msrs = cnl_features.has_nhm_msrs,
.has_config_tdp = cnl_features.has_config_tdp,
.bclk_freq = cnl_features.bclk_freq,
.supported_cstates = CC1 | CC6 | CC7 | PC2 | PC3 | PC6 | PC8 | PC10,
.cst_limit = cnl_features.cst_limit,
.has_irtl_msrs = cnl_features.has_irtl_msrs,
.has_msr_core_c1_res = cnl_features.has_msr_core_c1_res,
.has_ext_cst_msrs = cnl_features.has_ext_cst_msrs,
.trl_msrs = cnl_features.trl_msrs,
.tcc_offset_bits = cnl_features.tcc_offset_bits,
.rapl_msrs = cnl_features.rapl_msrs,
.enable_tsc_tweak = cnl_features.enable_tsc_tweak,
};
/* Copied from adl_features, with PC3/PC8 removed */
static const struct platform_features lnl_features = {
.has_msr_misc_feature_control = 1,
.has_msr_misc_pwr_mgmt = 1,
.has_nhm_msrs = 1,
.has_config_tdp = 1,
.bclk_freq = BCLK_100MHZ,
.supported_cstates = CC1 | CC6 | CC7 | PC2 | PC6 | PC10,
.cst_limit = CST_LIMIT_HSW,
.has_irtl_msrs = 1,
.has_msr_core_c1_res = 1,
.has_ext_cst_msrs = 1,
.trl_msrs = TRL_BASE,
.tcc_offset_bits = 6,
.rapl_msrs = RAPL_PKG_ALL | RAPL_CORE_ALL | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_GFX,
.enable_tsc_tweak = 1,
.has_msr_misc_feature_control = adl_features.has_msr_misc_feature_control,
.has_msr_misc_pwr_mgmt = adl_features.has_msr_misc_pwr_mgmt,
.has_nhm_msrs = adl_features.has_nhm_msrs,
.has_config_tdp = adl_features.has_config_tdp,
.bclk_freq = adl_features.bclk_freq,
.supported_cstates = CC1 | CC6 | CC7 | PC2 | PC6 | PC10,
.cst_limit = adl_features.cst_limit,
.has_irtl_msrs = adl_features.has_irtl_msrs,
.has_msr_core_c1_res = adl_features.has_msr_core_c1_res,
.has_ext_cst_msrs = adl_features.has_ext_cst_msrs,
.trl_msrs = adl_features.trl_msrs,
.tcc_offset_bits = adl_features.tcc_offset_bits,
.rapl_msrs = adl_features.rapl_msrs,
.enable_tsc_tweak = adl_features.enable_tsc_tweak,
};
static const struct platform_features skx_features = {