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cpufreq/amd-pstate: Rename MSR and shared memory specific functions
Existing function names "cppc_*" and "pstate_*" for shared memory and MSR based systems are not intuitive enough, replace them with "shmem_*" and "msr_*" respectively. Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://lore.kernel.org/r/20240917091434.10685-1-Dhananjay.Ugwekar@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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@ -233,7 +233,7 @@ static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata)
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return index;
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}
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static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
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static void msr_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
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u32 des_perf, u32 max_perf, bool fast_switch)
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{
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if (fast_switch)
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@ -243,7 +243,7 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
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READ_ONCE(cpudata->cppc_req_cached));
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}
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DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
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DEFINE_STATIC_CALL(amd_pstate_update_perf, msr_update_perf);
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static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
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u32 min_perf, u32 des_perf,
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@ -306,7 +306,7 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
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return ret;
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}
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static inline int pstate_enable(bool enable)
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static inline int msr_enable(bool enable)
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{
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int ret, cpu;
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unsigned long logical_proc_id_mask = 0;
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@ -332,7 +332,7 @@ static inline int pstate_enable(bool enable)
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return 0;
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}
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static int cppc_enable(bool enable)
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static int shmem_enable(bool enable)
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{
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int cpu, ret = 0;
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struct cppc_perf_ctrls perf_ctrls;
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@ -359,14 +359,14 @@ static int cppc_enable(bool enable)
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return ret;
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}
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DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
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DEFINE_STATIC_CALL(amd_pstate_enable, msr_enable);
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static inline int amd_pstate_enable(bool enable)
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{
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return static_call(amd_pstate_enable)(enable);
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}
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static int pstate_init_perf(struct amd_cpudata *cpudata)
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static int msr_init_perf(struct amd_cpudata *cpudata)
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{
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u64 cap1;
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@ -385,7 +385,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
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return 0;
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}
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static int cppc_init_perf(struct amd_cpudata *cpudata)
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static int shmem_init_perf(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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@ -420,14 +420,14 @@ static int cppc_init_perf(struct amd_cpudata *cpudata)
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return ret;
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}
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DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
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DEFINE_STATIC_CALL(amd_pstate_init_perf, msr_init_perf);
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static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
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{
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return static_call(amd_pstate_init_perf)(cpudata);
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}
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static void cppc_update_perf(struct amd_cpudata *cpudata,
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static void shmem_update_perf(struct amd_cpudata *cpudata,
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u32 min_perf, u32 des_perf,
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u32 max_perf, bool fast_switch)
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{
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@ -1897,9 +1897,9 @@ static int __init amd_pstate_init(void)
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current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
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} else {
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pr_debug("AMD CPPC shared memory based functionality is supported\n");
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static_call_update(amd_pstate_enable, cppc_enable);
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static_call_update(amd_pstate_init_perf, cppc_init_perf);
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static_call_update(amd_pstate_update_perf, cppc_update_perf);
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static_call_update(amd_pstate_enable, shmem_enable);
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static_call_update(amd_pstate_init_perf, shmem_init_perf);
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static_call_update(amd_pstate_update_perf, shmem_update_perf);
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}
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if (amd_pstate_prefcore) {
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