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Devicetree for v6.8:

Browse Source 
- Convert FPGA bridge, all TPMs (finally), and Rockchip HDMI bindings to
   schemas
 
 - Improvements in Samsung GPU schemas
 
 - A few more cases of dropping unneeded quotes in schemas
 
 - Merge QCom idle-states txt binding into common idle-states schema
 
 - Add X1E80100, SM8650, SM8650, and SDX75 SoCs to QCom Power Domain
   Controller
 
 - Add NXP i.mx8dl to SCU PD
 
 - Add synaptics r63353 panel controller
 
 - Clarify the wording around the use of 'wakeup-source' property
 
 - Add a DTS coding style doc
 
 - Add smi vendor prefix
 
 - Fix DT_SCHEMA_FILES incorrect matching of paths outside the kernel
   tree
 
 - Disable sysfb (e.g. EFI FB) when simple-framebuffer node is present
 
 - Fix double free in of_parse_phandle_with_args_map()
 
 - A couple of kerneldoc fixes
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Merge tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:

 - Convert FPGA bridge, all TPMs (finally), and Rockchip HDMI bindings
   to schemas

 - Improvements in Samsung GPU schemas

 - A few more cases of dropping unneeded quotes in schemas

 - Merge QCom idle-states txt binding into common idle-states schema

 - Add X1E80100, SM8650, SM8650, and SDX75 SoCs to QCom Power Domain
   Controller

 - Add NXP i.mx8dl to SCU PD

 - Add synaptics r63353 panel controller

 - Clarify the wording around the use of 'wakeup-source' property

 - Add a DTS coding style doc

 - Add smi vendor prefix

 - Fix DT_SCHEMA_FILES incorrect matching of paths outside the kernel
   tree

 - Disable sysfb (e.g. EFI FB) when simple-framebuffer node is present

 - Fix double free in of_parse_phandle_with_args_map()

 - A couple of kerneldoc fixes

* tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (37 commits)
  of: unittest: Fix of_count_phandle_with_args() expected value message
  dt-bindings: fpga: altera: Convert bridge bindings to yaml
  dt-bindings: fpga: Convert bridge binding to yaml
  dt-bindings: vendor-prefixes: Add smi
  dt-bindings: power: Clarify wording for wakeup-source property
  of: Fix double free in of_parse_phandle_with_args_map
  dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES
  drivers: of: Fixed kernel doc warning
  dt-bindings: tpm: Document Microsoft fTPM bindings
  dt-bindings: tpm: Convert IBM vTPM bindings to DT schema
  dt-bindings: tpm: Convert Google Cr50 bindings to DT schema
  dt-bindings: tpm: Consolidate TCG TIS bindings
  dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
  dt-bindings: arm: Add remote etm dt-binding
  dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo
  media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas
  dt-bindings: display: panel: Add synaptics r63353 panel controller
  dt-bindings: arm: merge qcom,idle-state with idle-state
  dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml
  dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries
  ...
This commit is contained in:
Linus Torvalds 2024-01-12 15:05:30 -08:00
commit 38814330fe
65 changed files with 1426 additions and 598 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/Makefile
View File

@ -28,7 +28,7 @@ $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' \)
find_cmd = $(find_all_cmd) | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))"
find_cmd = $(find_all_cmd) | sed 's|^$(srctree)/$(src)/||' | grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | sed 's|^|$(srctree)/$(src)/|'
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)

2
Documentation/devicetree/bindings/arm/calxeda/l2ecc.yaml
View File

@ -16,7 +16,7 @@ maintainers:
properties:
compatible:
const: "calxeda,hb-sregs-l2-ecc"
const: calxeda,hb-sregs-l2-ecc
reg:
maxItems: 1

84
Documentation/devicetree/bindings/arm/msm/qcom,idle-state.txt
View File

@ -1,84 +0,0 @@
QCOM Idle States for cpuidle driver
ARM provides idle-state node to define the cpuidle states, as defined in [1].
cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
states. Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
The idle-state for QCOM SoCs are distinguished by the compatible property of
the idle-states device node.
The devicetree representation of the idle state should be -
Required properties:
- compatible: Must be one of -
"qcom,idle-state-ret",
"qcom,idle-state-spc",
"qcom,idle-state-pc",
and "arm,idle-state".
Other required and optional properties are specified in [1].
Example:
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
[1]. Documentation/devicetree/bindings/cpu/idle-states.yaml

51
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml Normal file
View File

@ -0,0 +1,51 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/qcom,coresight-remote-etm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- Jinlong Mao <quic_jinlmao@quicinc.com>
- Tao Zhang <quic_taozha@quicinc.com>
description:
Support for ETM trace collection on remote processor using coresight
framework. Enabling this will allow turning on ETM tracing on remote
processor like modem processor via sysfs and collecting the trace
via coresight TMC sinks.
properties:
compatible:
const: qcom,coresight-remote-etm
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
additionalProperties: false
properties:
port:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- out-ports
additionalProperties: false
examples:
- |
etm {
compatible = "qcom,coresight-remote-etm";
out-ports {
port {
modem_etm0_out_funnel_modem: endpoint {
remote-endpoint = <&funnel_modem_in_modem_etm0>;
};
};
};
};
...

2
Documentation/devicetree/bindings/cache/qcom,llcc.yaml vendored
View File

@ -66,6 +66,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc7180-llcc
- qcom,sm6350-llcc
then:
@ -103,7 +104,6 @@ allOf:
compatible:
contains:
enum:
- qcom,qdu1000-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,x1e80100-llcc

77
Documentation/devicetree/bindings/cpu/idle-states.yaml
View File

@ -243,7 +243,64 @@ description: |+
just supports idle_standby, an idle-states node is not required.
===========================================
6 - References
6 - Qualcomm specific STATES
===========================================
Idle states have different enter/exit latency and residency values.
The idle states supported by the QCOM SoC are defined as -
* Standby
* Retention
* Standalone Power Collapse (Standalone PC or SPC)
* Power Collapse (PC)
Standby: Standby does a little more in addition to architectural clock gating.
When the WFI instruction is executed the ARM core would gate its internal
clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
trigger to execute the SPM state machine. The SPM state machine waits for the
interrupt to trigger the core back in to active. This triggers the cache
hierarchy to enter standby states, when all cpus are idle. An interrupt brings
the SPM state machine out of its wait, the next step is to ensure that the
cache hierarchy is also out of standby, and then the cpu is allowed to resume
execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
driver and is not defined in the DT. The SPM state machine should be
configured to execute this state by default and after executing every other
state below.
Retention: Retention is a low power state where the core is clock gated and
the memory and the registers associated with the core are retained. The
voltage may be reduced to the minimum value needed to keep the processor
registers active. The SPM should be configured to execute the retention
sequence and would wait for interrupt, before restoring the cpu to execution
state. Retention may have a slightly higher latency than Standby.
Standalone PC: A cpu can power down and warmboot if there is a sufficient time
between the time it enters idle and the next known wake up. SPC mode is used
to indicate a core entering a power down state without consulting any other
cpu or the system resources. This helps save power only on that core. The SPM
sequence for this idle state is programmed to power down the supply to the
core, wait for the interrupt, restore power to the core, and ensure the
system state including cache hierarchy is ready before allowing core to
resume. Applying power and resetting the core causes the core to warmboot
back into Elevation Level (EL) which trampolines the control back to the
kernel. Entering a power down state for the cpu, needs to be done by trapping
into a EL. Failing to do so, would result in a crash enforced by the warm boot
code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
be flushed in s/w, before powering down the core.
Power Collapse: This state is similar to the SPC mode, but distinguishes
itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
modes. In a hierarchical power domain SoC, this means L2 and other caches can
be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
voltages reduced, provided all cpus enter this state. Since the span of low
power modes possible at this state is vast, the exit latency and the residency
of this low power mode would be considered high even though at a cpu level,
this essentially is cpu power down. The SPM in this state also may handshake
with the Resource power manager (RPM) processor in the SoC to indicate a
complete application processor subsystem shut down.
===========================================
7 - References
===========================================
[1] ARM Linux Kernel documentation - CPUs bindings
@ -301,7 +358,14 @@ patternProperties:
properties:
compatible:
enum:
oneOf:
- items:
- enum:
- qcom,idle-state-ret
- qcom,idle-state-spc
- qcom,idle-state-pc
- const: arm,idle-state
- enum:
- arm,idle-state
- riscv,idle-state
@ -852,4 +916,13 @@ examples:
};
};
// Example 4 - Qualcomm SPC
idle-states {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc", "arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
...

61
Documentation/devicetree/bindings/display/panel/synaptics,r63353.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/synaptics,r63353.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synaptics R63353 based MIPI-DSI panels
maintainers:
- Michael Trimarchi <michael@amarulasolutions.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- sharp,ls068b3sx02
- const: syna,r63353
avdd-supply: true
dvdd-supply: true
reg: true
required:
- compatible
- avdd-supply
- dvdd-supply
- reg
- reset-gpios
- port
- backlight
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "sharp,ls068b3sx02", "syna,r63353";
reg = <0>;
avdd-supply = <&avdd_display>;
dvdd-supply = <&dvdd_display>;
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
};
};
...

49
Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt
View File

@ -1,49 +0,0 @@
Rockchip specific extensions to the Innosilicon HDMI
================================
Required properties:
- compatible:
"rockchip,rk3036-inno-hdmi";
- reg:
Physical base address and length of the controller's registers.
- clocks, clock-names:
Phandle to hdmi controller clock, name should be "pclk"
- interrupts:
HDMI interrupt number
- ports:
Contain one port node with endpoint definitions as defined in
Documentation/devicetree/bindings/graph.txt.
- pinctrl-0, pinctrl-name:
Switch the iomux of HPD/CEC pins to HDMI function.
Example:
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_lcdc: endpoint@0 {
reg = <0>;
remote-endpoint = <&lcdc_out_hdmi>;
};
};
};
&pinctrl {
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
<1 9 RK_FUNC_1 &pcfg_pull_none>,
<1 10 RK_FUNC_1 &pcfg_pull_none>,
<1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
};

139
Documentation/devicetree/bindings/display/rockchip/rockchip,inno-hdmi.yaml Normal file
View File

@ -0,0 +1,139 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip,inno-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip Innosilicon HDMI controller
maintainers:
- Sandy Huang <hjc@rock-chips.com>
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3036-inno-hdmi
- rockchip,rk3128-inno-hdmi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
items:
- description: The HDMI controller main clock
- description: The HDMI PHY reference clock
clock-names:
minItems: 1
items:
- const: pclk
- const: ref
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to a vop node.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Port node with one endpoint connected to a hdmi-connector node.
required:
- port@0
- port@1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- pinctrl-0
- pinctrl-names
- ports
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3036-inno-hdmi
then:
properties:
power-domains: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3128-inno-hdmi
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
required:
- power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in: port@0 {
reg = <0>;
hdmi_in_vop: endpoint {
remote-endpoint = <&vop_out_hdmi>;
};
};
hdmi_out: port@1 {
reg = <1>;
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
};
};
pinctrl {
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
<1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>,
<1 RK_PB3 1 &pcfg_pull_none>;
};
};
};

196
Documentation/devicetree/bindings/dts-coding-style.rst Normal file
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@ -0,0 +1,196 @@
.. SPDX-License-Identifier: GPL-2.0
=====================================
Devicetree Sources (DTS) Coding Style
=====================================
When writing Devicetree Sources (DTS) please observe below guidelines. They
should be considered complementary to any rules expressed already in
the Devicetree Specification and the dtc compiler (including W=1 and W=2
builds).
Individual architectures and subarchitectures can define additional rules,
making the coding style stricter.
Naming and Valid Characters
---------------------------
The Devicetree Specification allows a broad range of characters in node
and property names, but this coding style narrows the range down to achieve
better code readability.
1. Node and property names can use only the following characters:
* Lowercase characters: [a-z]
* Digits: [0-9]
* Dash: -
2. Labels can use only the following characters:
* Lowercase characters: [a-z]
* Digits: [0-9]
* Underscore: _
3. Unless a bus defines differently, unit addresses shall use lowercase
hexadecimal digits, without leading zeros (padding).
4. Hex values in properties, e.g. "reg", shall use lowercase hex. The address
part can be padded with leading zeros.
Example::
gpi_dma2: dma-controller@a00000 {
compatible = "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0x0 0x00a00000 0x0 0x60000>;
}
Order of Nodes
--------------
1. Nodes on any bus, thus using unit addresses for children, shall be
ordered by unit address in ascending order.
Alternatively for some subarchitectures, nodes of the same type can be
grouped together, e.g. all I2C controllers one after another even if this
breaks unit address ordering.
2. Nodes without unit addresses shall be ordered alpha-numerically by the node
name. For a few node types, they can be ordered by the main property, e.g.
pin configuration states ordered by value of "pins" property.
3. When extending nodes in the board DTS via &label, the entries shall be
ordered either alpha-numerically or by keeping the order from DTSI, where
the choice depends on the subarchitecture.
The above-described ordering rules are easy to enforce during review, reduce
chances of conflicts for simultaneous additions of new nodes to a file and help
in navigating through the DTS source.
Example::
/* SoC DTSI */
/ {
cpus {
/* ... */
};
psci {
/* ... */
};
soc@0 {
dma: dma-controller@10000 {
/* ... */
};
clk: clock-controller@80000 {
/* ... */
};
};
};
/* Board DTS - alphabetical order */
&clk {
/* ... */
};
&dma {
/* ... */
};
/* Board DTS - alternative order, keep as DTSI */
&dma {
/* ... */
};
&clk {
/* ... */
};
Order of Properties in Device Node
----------------------------------
The following order of properties in device nodes is preferred:
1. "compatible"
2. "reg"
3. "ranges"
4. Standard/common properties (defined by common bindings, e.g. without
vendor-prefixes)
5. Vendor-specific properties
6. "status" (if applicable)
7. Child nodes, where each node is preceded with a blank line
The "status" property is by default "okay", thus it can be omitted.
The above-described ordering follows this approach:
1. Most important properties start the node: compatible then bus addressing to
match unit address.
2. Each node will have common properties in similar place.
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
Example::
/* SoC DTSI */
device_node: device-class@6789abc {
compatible = "vendor,device";
reg = <0x0 0x06789abc 0x0 0xa123>;
ranges = <0x0 0x0 0x06789abc 0x1000>;
#dma-cells = <1>;
clocks = <&clock_controller 0>, <&clock_controller 1>;
clock-names = "bus", "host";
vendor,custom-property = <2>;
status = "disabled";
child_node: child-class@100 {
reg = <0x100 0x200>;
/* ... */
};
};
/* Board DTS */
&device_node {
vdd-supply = <&board_vreg1>;
status = "okay";
}
Indentation
-----------
1. Use indentation according to Documentation/process/coding-style.rst.
2. Each entry in arrays with multiple cells, e.g. "reg" with two IO addresses,
shall be enclosed in <>.
3. For arrays spanning across lines, it is preferred to align the continued
entries with opening < from the first line.
Example::
thermal-sensor@c271000 {
compatible = "qcom,sm8550-tsens", "qcom,tsens-v2";
reg = <0x0 0x0c271000 0x0 0x1000>,
<0x0 0x0c222000 0x0 0x1000>;
};
Organizing DTSI and DTS
-----------------------
The DTSI and DTS files shall be organized in a way representing the common,
reusable parts of hardware. Typically, this means organizing DTSI and DTS files
into several files:
1. DTSI with contents of the entire SoC, without nodes for hardware not present
on the SoC.
2. If applicable: DTSI with common or re-usable parts of the hardware, e.g.
entire System-on-Module.
3. DTS representing the board.
Hardware components that are present on the board shall be placed in the
board DTS, not in the SoC or SoM DTSI. A partial exception is a common
external reference SoC input clock, which could be coded as a fixed-clock in
the SoC DTSI with its frequency provided by each board DTS.

13
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@ -1,13 +0,0 @@
Altera FPGA To SDRAM Bridge Driver
Required properties:
- compatible : Should contain "altr,socfpga-fpga2sdram-bridge"
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
fpga_bridge3: fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

20
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@ -1,20 +0,0 @@
Altera Freeze Bridge Controller Driver
The Altera Freeze Bridge Controller manages one or more freeze bridges.
The controller can freeze/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
unfreeze/enable the bridges which allows traffic to pass through the
bridge normally.
Required properties:
- compatible : Should contain "altr,freeze-bridge-controller"
- regs : base address and size for freeze bridge module
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
freeze-controller@100000450 {
compatible = "altr,freeze-bridge-controller";
regs = <0x1000 0x10>;
bridge-enable = <0>;
};

36
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@ -1,36 +0,0 @@
Altera FPGA/HPS Bridge Driver
Required properties:
- regs : base address and size for AXI bridge module
- compatible : Should contain one of:
"altr,socfpga-lwhps2fpga-bridge",
"altr,socfpga-hps2fpga-bridge", or
"altr,socfpga-fpga2hps-bridge"
- resets : Phandle and reset specifier for this bridge's reset
- clocks : Clocks used by this module.
See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <0>;
};
fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
bridge-enable = <1>;
};
fpga_bridge2: fpga-bridge@ff600000 {
compatible = "altr,socfpga-fpga2hps-bridge";
reg = <0xff600000 0x100000>;
resets = <&rst FPGA2HPS_RESET>;
clocks = <&l4_main_clk>;
};

41
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@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera Freeze Bridge Controller
description:
The Altera Freeze Bridge Controller manages one or more freeze bridges.
The controller can freeze/disable the bridges which prevents signal
changes from passing through the bridge. The controller can also
unfreeze/enable the bridges which allows traffic to pass through the bridge
normally.
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
const: altr,freeze-bridge-controller
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
fpga-bridge@100000450 {
compatible = "altr,freeze-bridge-controller";
reg = <0x1000 0x10>;
bridge-enable = <0>;
};

33
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@ -0,0 +1,33 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera FPGA To SDRAM Bridge
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
const: altr,socfpga-fpga2sdram-bridge
reg:
maxItems: 1
required:
- compatible
unevaluatedProperties: false
examples:
- |
fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

49
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@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera FPGA/HPS Bridge
maintainers:
- Xu Yilun <yilun.xu@intel.com>
allOf:
- $ref: fpga-bridge.yaml#
properties:
compatible:
enum:
- altr,socfpga-lwhps2fpga-bridge
- altr,socfpga-hps2fpga-bridge
- altr,socfpga-fpga2hps-bridge
reg:
maxItems: 1
resets:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- clocks
- resets
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/reset/altr,rst-mgr.h>
fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
bridge-enable = <0>;
clocks = <&l4_main_clk>;
resets = <&rst LWHPS2FPGA_RESET>;
};

13
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@ -1,13 +0,0 @@
FPGA Bridge Device Tree Binding
Optional properties:
- bridge-enable : 0 if driver should disable bridge at startup
1 if driver should enable bridge at startup
Default is to leave bridge in current state.
Example:
fpga_bridge3: fpga-bridge@ffc25080 {
compatible = "altr,socfpga-fpga2sdram-bridge";
reg = <0xffc25080 0x4>;
bridge-enable = <0>;
};

30
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@ -0,0 +1,30 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FPGA Bridge
maintainers:
- Michal Simek <michal.simek@amd.com>
properties:
$nodename:
pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
bridge-enable:
description: |
0 if driver should disable bridge at startup
1 if driver should enable bridge at startup
Default is to leave bridge in current state.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
additionalProperties: true
examples:
- |
fpga-bridge {
bridge-enable = <0>;
};

5
Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml
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@ -9,6 +9,9 @@ title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
maintainers:
- Nava kishore Manne <nava.kishore.manne@amd.com>
allOf:
- $ref: fpga-bridge.yaml#
description: |
The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
decouplers/fpga bridges. The controller can decouple/disable the bridges
@ -51,7 +54,7 @@ required:
- clocks
- clock-names
additionalProperties: false
unevaluatedProperties: false
examples:
- |

39
Documentation/devicetree/bindings/gpu/samsung-g2d.yaml
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@ -22,18 +22,36 @@ properties:
interrupts:
maxItems: 1
clocks: {}
clock-names: {}
iommus: {}
power-domains: {}
clocks:
minItems: 1
maxItems: 2
if:
clock-names:
minItems: 1
maxItems: 2
iommus:
minItems: 1
maxItems: 2
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5250-g2d
then:
then:
properties:
clocks:
items:
@ -42,7 +60,7 @@ then:
items:
- const: fimg2d
else:
else:
properties:
clocks:
items:
@ -53,13 +71,6 @@ else:
- const: sclk_fimg2d
- const: fimg2d
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:

9
Documentation/devicetree/bindings/gpu/samsung-rotator.yaml
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@ -12,10 +12,11 @@ maintainers:
properties:
compatible:
enum:
- "samsung,s5pv210-rotator"
- "samsung,exynos4210-rotator"
- "samsung,exynos4212-rotator"
- "samsung,exynos5250-rotator"
- samsung,s5pv210-rotator
- samsung,exynos4210-rotator
- samsung,exynos4212-rotator
- samsung,exynos5250-rotator
reg:
maxItems: 1

71
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@ -21,40 +21,20 @@ properties:
interrupts:
maxItems: 1
clocks: {}
clock-names: {}
iommus: {}
power-domains: {}
if:
properties:
compatible:
contains:
const: samsung,exynos5420-scaler
then:
properties:
clocks:
items:
- description: mscl clock
minItems: 1
maxItems: 3
clock-names:
items:
- const: mscl
minItems: 1
maxItems: 3
else:
properties:
clocks:
items:
- description: pclk clock
- description: aclk clock
- description: aclk_xiu clock
iommus:
minItems: 1
maxItems: 2
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
power-domains:
maxItems: 1
required:
- compatible
@ -63,6 +43,39 @@ required:
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5420-scaler
then:
properties:
clocks:
items:
- description: mscl clock
clock-names:
items:
- const: mscl
iommus:
minItems: 2
else:
properties:
clocks:
items:
- description: pclk clock
- description: aclk clock
- description: aclk_xiu clock
clock-names:
items:
- const: pclk
- const: aclk
- const: aclk_xiu
iommus:
maxItems: 1
additionalProperties: false
examples:

1
Documentation/devicetree/bindings/index.rst
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@ -4,6 +4,7 @@
:maxdepth: 1
ABI
dts-coding-style
writing-bindings
writing-schema
submitting-patches

4
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
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@ -35,12 +35,16 @@ properties:
- qcom,sdm845-pdc
- qcom,sdx55-pdc
- qcom,sdx65-pdc
- qcom,sdx75-pdc
- qcom,sm4450-pdc
- qcom,sm6350-pdc
- qcom,sm8150-pdc
- qcom,sm8250-pdc
- qcom,sm8350-pdc
- qcom,sm8450-pdc
- qcom,sm8550-pdc
- qcom,sm8650-pdc
- qcom,x1e80100-pdc
- const: qcom,pdc
reg:

33
Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
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@ -50,7 +50,9 @@ properties:
iommu-names:
minItems: 1
maxItems: 2
items:
- const: left
- const: right
power-domains:
maxItems: 1
@ -85,7 +87,7 @@ allOf:
- const: sclk_mfc
iommus:
maxItems: 1
iommus-names: false
iommu-names: false
- if:
properties:
@ -103,11 +105,9 @@ allOf:
- const: aclk
- const: aclk_xiu
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
minItems: 2
iommu-names:
minItems: 2
- if:
properties:
@ -124,11 +124,9 @@ allOf:
- const: mfc
- const: sclk_mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
minItems: 2
iommu-names:
minItems: 2
- if:
properties:
@ -145,11 +143,9 @@ allOf:
items:
- const: mfc
iommus:
maxItems: 2
iommus-names:
items:
- const: left
- const: right
minItems: 2
iommu-names:
minItems: 2
- if:
properties:
@ -162,9 +158,6 @@ allOf:
clocks:
minItems: 1
maxItems: 2
iommus:
minItems: 1
maxItems: 2
- if:
properties:

2
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@ -12,7 +12,7 @@ maintainers:
properties:
compatible:
const: "fsl,dpaa2-console"
const: fsl,dpaa2-console
reg:
maxItems: 1

4
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@ -18,7 +18,7 @@ allOf:
const: marvell,armada-380-sdhci
then:
properties:
regs:
reg:
minItems: 3
reg-names:
minItems: 3
@ -26,7 +26,7 @@ allOf:
- reg-names
else:
properties:
regs:
reg:
maxItems: 1
reg-names:
maxItems: 1

1
Documentation/devicetree/bindings/power/fsl,scu-pd.yaml
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@ -20,6 +20,7 @@ properties:
compatible:
items:
- enum:
- fsl,imx8dl-scu-pd
- fsl,imx8qm-scu-pd
- fsl,imx8qxp-scu-pd
- const: fsl,scu-pd

18
Documentation/devicetree/bindings/power/wakeup-source.txt
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@ -3,16 +3,20 @@ Specifying wakeup capability for devices
Any device nodes
----------------
Nodes that describe devices which has wakeup capability must contain an
Nodes that describe devices which have wakeup capability may contain a
"wakeup-source" boolean property.
Also, if device is marked as a wakeup source, then all the primary
interrupt(s) can be used as wakeup interrupt(s).
If the device is marked as a wakeup-source, interrupt wake capability depends
on the device specific "interrupt-names" property. If no interrupts are labeled
as wake capable, then it is up to the device to determine which interrupts can
wake the system.
However if the devices have dedicated interrupt as the wakeup source
then they need to specify/identify the same using device specific
interrupt name. In such cases only that interrupt can be used as wakeup
interrupt.
However if a device has a dedicated interrupt as the wakeup source, then it
needs to specify/identify it using a device specific interrupt name. In such
cases only that interrupt can be used as a wakeup interrupt.
While various legacy interrupt names exist, new devices should use "wakeup" as
the canonical interrupt name.
List of legacy properties and respective binding document
---------------------------------------------------------

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@ -1,19 +0,0 @@
* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
H1 Secure Microcontroller running Cr50 firmware provides several
functions, including TPM-like functionality. It communicates over
SPI using the FIFO protocol described in the PTP Spec, section 6.
Required properties:
- compatible: Should be "google,cr50".
- spi-max-frequency: Maximum SPI frequency.
Example:
&spi0 {
tpm@0 {
compatible = "google,cr50";
reg = <0>;
spi-max-frequency = <800000>;
};
};

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@ -1,41 +0,0 @@
* Device Tree Bindings for IBM Virtual Trusted Platform Module(vtpm)
Required properties:
- compatible : property name that conveys the platform architecture
identifiers, as 'IBM,vtpm'
- device_type : specifies type of virtual device
- interrupts : property specifying the interrupt source number and
sense code associated with this virtual I/O Adapters
- ibm,my-drc-index : integer index for the connector between the device
and its parent - present only if Dynamic
Reconfiguration(DR) Connector is enabled
- ibm,#dma-address-cells: specifies the number of cells that are used to
encode the physical address field of dma-window
properties
- ibm,#dma-size-cells : specifies the number of cells that are used to
encode the size field of dma-window properties
- ibm,my-dma-window : specifies DMA window associated with this virtual
IOA
- ibm,loc-code : specifies the unique and persistent location code
associated with this virtual I/O Adapters
- linux,sml-base : 64-bit base address of the reserved memory allocated
for the firmware event log
- linux,sml-size : size of the memory allocated for the firmware event log
Example (IBM Virtual Trusted Platform Module)
---------------------------------------------
vtpm@30000003 {
ibm,#dma-size-cells = <0x2>;
compatible = "IBM,vtpm";
device_type = "IBM,vtpm";
ibm,my-drc-index = <0x30000003>;
ibm,#dma-address-cells = <0x2>;
linux,sml-base = <0xc60e 0x0>;
interrupts = <0xa0003 0x0>;
ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>;
ibm,loc-code = "U8286.41A.10082DV-V3-C3";
reg = <0x30000003>;
linux,sml-size = <0xbce10200>;
};

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@ -1,34 +0,0 @@
* STMicroelectronics SAS. ST33ZP24 TPM SoC
Required properties:
- compatible: Should be "st,st33zp24-i2c".
- clock-frequency: I²C work frequency.
- reg: address on the bus
Optional ST33ZP24 Properties:
- interrupts: GPIO interrupt to which the chip is connected
- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
If set, power must be present when the platform is going into sleep/hibernate mode.
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
Example (for ARM-based BeagleBoard xM with ST33ZP24 on I2C2):
&i2c2 {
st33zp24: st33zp24@13 {
compatible = "st,st33zp24-i2c";
reg = <0x13>;
clock-frequency = <400000>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};

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@ -1,32 +0,0 @@
* STMicroelectronics SAS. ST33ZP24 TPM SoC
Required properties:
- compatible: Should be "st,st33zp24-spi".
- spi-max-frequency: Maximum SPI frequency (<= 10000000).
Optional ST33ZP24 Properties:
- interrupts: GPIO interrupt to which the chip is connected
- lpcpd-gpios: Output GPIO pin used for ST33ZP24 power management D1/D2 state.
If set, power must be present when the platform is going into sleep/hibernate mode.
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
Example (for ARM-based BeagleBoard xM with ST33ZP24 on SPI4):
&mcspi4 {
st33zp24@0 {
compatible = "st,st33zp24-spi";
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};

26
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@ -1,26 +0,0 @@
* Device Tree Bindings for I2C based Trusted Platform Module(TPM)
Required properties:
- compatible : 'manufacturer,model', eg. nuvoton,npct650
- label : human readable string describing the device, eg. "tpm"
- linux,sml-base : 64-bit base address of the reserved memory allocated for
the firmware event log
- linux,sml-size : size of the memory allocated for the firmware event log
Optional properties:
- powered-while-suspended: present when the TPM is left powered on between
suspend and resume (makes the suspend/resume
callbacks do nothing).
Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C)
----------------------------------------------------------
tpm@57 {
reg = <0x57>;
label = "tpm";
compatible = "nuvoton,npct650", "nuvoton,npct601";
linux,sml-base = <0x7f 0xfd450000>;
linux,sml-size = <0x10000>;
};

25
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@ -1,25 +0,0 @@
Trusted Computing Group MMIO Trusted Platform Module
The TCG defines multi vendor standard for accessing a TPM chip, this
is the standard protocol defined to access the TPM via MMIO. Typically
this interface will be implemented over Intel's LPC bus.
Refer to the 'TCG PC Client Specific TPM Interface Specification (TIS)' TCG
publication for the specification.
Required properties:
- compatible: should contain a string below for the chip, followed by
"tcg,tpm-tis-mmio". Valid chip strings are:
* "atmel,at97sc3204"
- reg: The location of the MMIO registers, should be at least 0x5000 bytes
- interrupts: An optional interrupt indicating command completion.
Example:
tpm_tis@90000 {
compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
reg = <0x90000 0x5000>;
interrupt-parent = <&EIC0>;
interrupts = <1 2>;
};

23
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@ -1,23 +0,0 @@
Required properties:
- compatible: should be one of the following
"st,st33htpm-spi"
"infineon,slb9670"
"tcg,tpm_tis-spi"
- spi-max-frequency: Maximum SPI frequency (depends on TPMs).
Optional SoC Specific Properties:
- pinctrl-names: Contains only one value - "default".
- pintctrl-0: Specifies the pin control groups used for this controller.
Example (for ARM-based BeagleBoard xM with TPM_TIS on SPI4):
&mcspi4 {
tpm_tis@0 {
compatible = "tcg,tpm_tis-spi";
spi-max-frequency = <10000000>;
};
};

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@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Google Security Chip H1 (running Cr50 firmware)
maintainers:
- Andrey Pronin <apronin@chromium.org>
description: |
Google has designed a family of security chips called "Titan".
One member is the H1 built into Chromebooks and running Cr50 firmware:
https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/
The chip provides several functions, including TPM 2.0 like functionality.
It communicates over SPI or I²C using the FIFO protocol described in the
TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:
https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
properties:
compatible:
const: google,cr50
allOf:
- $ref: tpm-common.yaml#
anyOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- $ref: tcg,tpm-tis-i2c.yaml#/properties/reg
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
tpm@0 {
reg = <0>;
compatible = "google,cr50";
spi-max-frequency = <800000>;
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
tpm@50 {
compatible = "google,cr50";
reg = <0x50>;
interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&cr50_int>;
};
};

104
Documentation/devicetree/bindings/tpm/ibm,vtpm.yaml Normal file
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@ -0,0 +1,104 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/ibm,vtpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: IBM Virtual Trusted Platform Module (vTPM)
maintainers:
- Nayna Jain <nayna@linux.ibm.com>
description: |
Virtual TPM is used on IBM POWER7+ and POWER8 systems running POWERVM.
It is supported through the adjunct partition with firmware release 740
or higher. With vTPM support, each lpar is able to have its own vTPM
without the physical TPM hardware. The TPM functionality is provided by
communicating with the vTPM adjunct partition through Hypervisor calls
(Hcalls) and Command/Response Queue (CRQ) commands.
properties:
compatible:
enum:
- IBM,vtpm
- IBM,vtpm20
device_type:
description:
type of virtual device
enum:
- IBM,vtpm
- IBM,vtpm20
reg:
maxItems: 1
'ibm,#dma-address-cells':
description:
number of cells that are used to encode the physical address field of
dma-window properties
$ref: /schemas/types.yaml#/definitions/uint32-array
'ibm,#dma-size-cells':
description:
number of cells that are used to encode the size field of
dma-window properties
$ref: /schemas/types.yaml#/definitions/uint32-array
ibm,my-dma-window:
description:
DMA window associated with this virtual I/O Adapter
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 5
maxItems: 5
ibm,my-drc-index:
description:
integer index for the connector between the device and its parent;
present only if Dynamic Reconfiguration (DR) Connector is enabled
$ref: /schemas/types.yaml#/definitions/uint32
ibm,loc-code:
description:
unique and persistent location code associated with this virtual
I/O Adapter
$ref: /schemas/types.yaml#/definitions/string
required:
- compatible
- device_type
- reg
- interrupts
- ibm,#dma-address-cells
- ibm,#dma-size-cells
- ibm,my-dma-window
- ibm,my-drc-index
- ibm,loc-code
- linux,sml-base
- linux,sml-size
allOf:
- $ref: tpm-common.yaml#
unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <1>;
#size-cells = <0>;
tpm@30000003 {
compatible = "IBM,vtpm";
device_type = "IBM,vtpm";
reg = <0x30000003>;
interrupts = <0xa0003 0x0>;
ibm,#dma-address-cells = <0x2>;
ibm,#dma-size-cells = <0x2>;
ibm,my-dma-window = <0x10000003 0x0 0x0 0x0 0x10000000>;
ibm,my-drc-index = <0x30000003>;
ibm,loc-code = "U8286.41A.10082DV-V3-C3";
linux,sml-base = <0xc60e 0x0>;
linux,sml-size = <0xbce10200>;
};
};

47
Documentation/devicetree/bindings/tpm/microsoft,ftpm.yaml Normal file
View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/microsoft,ftpm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsoft firmware-based Trusted Platform Module (fTPM)
maintainers:
- Thirupathaiah Annapureddy <thiruan@microsoft.com>
- Sasha Levin <sashal@kernel.org>
description: |
Commodity CPU architectures, such as ARM and Intel CPUs, have started to
offer trusted computing features in their CPUs aimed at displacing dedicated
trusted hardware. Unfortunately, these CPU architectures raise serious
challenges to building trusted systems because they omit providing secure
resources outside the CPU perimeter.
Microsoft's firmware-based TPM 2.0 (fTPM) leverages ARM TrustZone to overcome
these challenges and provide software with security guarantees similar to
those of dedicated trusted hardware.
https://www.microsoft.com/en-us/research/publication/ftpm-software-implementation-tpm-chip/
https://github.com/Microsoft/ms-tpm-20-ref/tree/main/Samples/ARM32-FirmwareTPM
properties:
compatible:
const: microsoft,ftpm
required:
- compatible
- linux,sml-base
- linux,sml-size
allOf:
- $ref: tpm-common.yaml#
unevaluatedProperties: false
examples:
- |
tpm {
compatible = "microsoft,ftpm";
linux,sml-base = <0x0 0xc0000000>;
linux,sml-size = <0x10000>;
};

90
Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml Normal file
View File

@ -0,0 +1,90 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: I²C-attached Trusted Platform Module conforming to TCG TIS specification
maintainers:
- Lukas Wunner <lukas@wunner.de>
description: |
The Trusted Computing Group (TCG) has defined a multi-vendor standard
for accessing a TPM chip. It can be transported over various buses,
one of them being I²C. The standard is named:
TCG PC Client Specific TPM Interface Specification (TIS)
https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
The I²C interface was not originally part of the standard, but added
in 2017 with a separate document:
TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP)
https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
Recent TPM 2.0 chips conform to this generic interface, others use a
vendor-specific I²C interface.
properties:
compatible:
oneOf:
- description: Generic TPM 2.0 chips conforming to TCG PTP interface
items:
- enum:
- infineon,slb9673
- nuvoton,npct75x
- const: tcg,tpm-tis-i2c
- description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface
items:
- enum:
- atmel,at97sc3204t # TPM 1.2
- infineon,slb9635tt # TPM 1.2 (maximum 100 kHz)
- infineon,slb9645tt # TPM 1.2 (maximum 400 kHz)
- infineon,tpm_i2c_infineon # TPM 1.2
- nuvoton,npct501 # TPM 1.2
- nuvoton,npct601 # TPM 2.0
- st,st33zp24-i2c # TPM 2.0
- winbond,wpct301 # TPM 1.2
reg:
description: address of TPM on the I²C bus
allOf:
- $ref: tpm-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
tpm@57 {
label = "tpm";
compatible = "nuvoton,npct601";
reg = <0x57>;
linux,sml-base = <0x7f 0xfd450000>;
linux,sml-size = <0x10000>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
tpm@13 {
reg = <0x13>;
compatible = "st,st33zp24-i2c";
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};

49
Documentation/devicetree/bindings/tpm/tcg,tpm-tis-mmio.yaml Normal file
View File

@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/tcg,tpm-tis-mmio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MMIO-accessed Trusted Platform Module conforming to TCG TIS specification
maintainers:
- Lukas Wunner <lukas@wunner.de>
description: |
The Trusted Computing Group (TCG) has defined a multi-vendor standard
for accessing a TPM chip. It can be transported over various buses,
one of them being LPC (via MMIO). The standard is named:
TCG PC Client Specific TPM Interface Specification (TIS)
https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
properties:
compatible:
items:
- enum:
- at97sc3201
- atmel,at97sc3204
- socionext,synquacer-tpm-mmio
- const: tcg,tpm-tis-mmio
reg:
description:
location and length of the MMIO registers, length should be
at least 0x5000 bytes
allOf:
- $ref: tpm-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
tpm@90000 {
compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
reg = <0x90000 0x5000>;
interrupt-parent = <&EIC0>;
interrupts = <1 2>;
};

75
Documentation/devicetree/bindings/tpm/tcg,tpm_tis-spi.yaml Normal file
View File

@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SPI-attached Trusted Platform Module conforming to TCG TIS specification
maintainers:
- Lukas Wunner <lukas@wunner.de>
description: |
The Trusted Computing Group (TCG) has defined a multi-vendor standard
for accessing a TPM chip. It can be transported over various buses,
one of them being SPI. The standard is named:
TCG PC Client Specific TPM Interface Specification (TIS)
https://trustedcomputinggroup.org/resource/pc-client-work-group-pc-client-specific-tpm-interface-specification-tis/
properties:
compatible:
items:
- enum:
- infineon,slb9670
- st,st33htpm-spi
- st,st33zp24-spi
- const: tcg,tpm_tis-spi
allOf:
- $ref: tpm-common.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
- if:
properties:
compatible:
contains:
const: st,st33zp24-spi
then:
properties:
spi-max-frequency:
maximum: 10000000
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
tpm@0 {
reg = <0>;
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
spi-max-frequency = <10000000>;
};
};
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
tpm@0 {
reg = <0>;
compatible = "st,st33zp24-spi", "tcg,tpm_tis-spi";
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio5>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
lpcpd-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
};
};

87
Documentation/devicetree/bindings/tpm/tpm-common.yaml Normal file
View File

@ -0,0 +1,87 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/tpm/tpm-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Trusted Platform Module common properties
maintainers:
- Lukas Wunner <lukas@wunner.de>
properties:
$nodename:
pattern: '^tpm(@[0-9a-f]+)?$'
interrupts:
description: indicates command completion
maxItems: 1
label:
description: human readable string describing the device, e.g. "tpm"
linux,sml-base:
description:
base address of reserved memory allocated for firmware event log
$ref: /schemas/types.yaml#/definitions/uint64
linux,sml-size:
description:
size of reserved memory allocated for firmware event log
$ref: /schemas/types.yaml#/definitions/uint32
memory-region:
description: reserved memory allocated for firmware event log
maxItems: 1
powered-while-suspended:
description:
present when the TPM is left powered on between suspend and resume
(makes the suspend/resume callbacks do nothing)
type: boolean
resets:
description: Reset controller to reset the TPM
$ref: /schemas/types.yaml#/definitions/phandle
reset-gpios:
description: Output GPIO pin to reset the TPM
maxItems: 1
# must always have both linux,sml-base and linux,sml-size
dependentRequired:
linux,sml-base: ['linux,sml-size']
linux,sml-size: ['linux,sml-base']
# must only have either memory-region or linux,sml-base
# as well as either resets or reset-gpios
dependentSchemas:
memory-region:
properties:
linux,sml-base: false
linux,sml-base:
properties:
memory-region: false
resets:
properties:
reset-gpios: false
reset-gpios:
properties:
resets: false
allOf:
- if:
properties:
compatible:
contains:
pattern: '^st,st33zp24'
then:
properties:
lpcpd-gpios:
description:
Output GPIO pin used for ST33ZP24 power management of D1/D2 state.
If set, power must be present when the platform is going into
sleep/hibernate mode.
maxItems: 1
additionalProperties: true

16
Documentation/devicetree/bindings/trivial-devices.yaml
View File

@ -49,8 +49,6 @@ properties:
- ams,iaq-core
# i2c serial eeprom (24cxx)
- at,24c08
# i2c trusted platform module (TPM)
- atmel,at97sc3204t
# ATSHA204 - i2c h/w symmetric crypto module
- atmel,atsha204
# ATSHA204A - i2c h/w symmetric crypto module
@ -151,12 +149,6 @@ properties:
- infineon,ir38263
# Infineon IRPS5401 Voltage Regulator (PMIC)
- infineon,irps5401
# Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
- infineon,slb9635tt
# Infineon SLB9645 I2C TPM (new protocol, max 400khz)
- infineon,slb9645tt
# Infineon SLB9673 I2C TPM 2.0
- infineon,slb9673
# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
- infineon,tlv493d-a1b6
# Infineon Multi-phase Digital VR Controller xdpe11280
@ -307,10 +299,6 @@ properties:
- national,lm85
# I2C ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator
- national,lm92
# i2c trusted platform module (TPM)
- nuvoton,npct501
# i2c trusted platform module (TPM2)
- nuvoton,npct601
# Nuvoton Temperature Sensor
- nuvoton,w83773g
# OKI ML86V7667 video decoder
@ -355,8 +343,6 @@ properties:
- silabs,si7020
# Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
- skyworks,sky81452
# Socionext SynQuacer TPM MMIO module
- socionext,synquacer-tpm-mmio
# SparkFun Qwiic Joystick (COM-15168) with i2c interface
- sparkfun,qwiic-joystick
# i2c serial eeprom (24cxx)
@ -411,8 +397,6 @@ properties:
- winbond,w83793
# Vicor Corporation Digital Supervisor
- vicor,pli1209bc
# i2c trusted platform module (TPM)
- winbond,wpct301
required:
- compatible

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -1295,6 +1295,8 @@ patternProperties:
description: Skyworks Solutions, Inc.
"^smartlabs,.*":
description: SmartLabs LLC
"^smi,.*":
description: Silicon Motion Technology Corporation
"^smsc,.*":
description: Standard Microsystems Corporation
"^snps,.*":

1
drivers/of/base.c
View File

@ -1464,6 +1464,7 @@ int of_parse_phandle_with_args_map(const struct device_node *np,
out_args->np = new;
of_node_put(cur);
cur = new;
new = NULL;
}
put:
of_node_put(cur);

2
drivers/of/overlay.c
View File

@ -964,7 +964,7 @@ static int of_overlay_apply(struct overlay_changeset *ovcs,
return ret;
}
/*
/**
* of_overlay_fdt_apply() - Create and apply an overlay changeset
* @overlay_fdt: pointer to overlay FDT
* @overlay_fdt_size: number of bytes in @overlay_fdt

18
drivers/of/platform.c
View File

@ -20,6 +20,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sysfb.h>
#include "of_private.h"
@ -621,8 +622,21 @@ static int __init of_platform_default_populate_init(void)
}
node = of_get_compatible_child(of_chosen, "simple-framebuffer");
if (node) {
/*
* Since a "simple-framebuffer" device is already added
* here, disable the Generic System Framebuffers (sysfb)
* to prevent it from registering another device for the
* system framebuffer later (e.g: using the screen_info
* data that may had been filled as well).
*
* This can happen for example on DT systems that do EFI
* booting and may provide a GOP handle to the EFI stub.
*/
sysfb_disable();
of_platform_device_create(node, NULL, NULL);
of_node_put(node);
}
/* Populate everything else. */
of_platform_default_populate(NULL, NULL, NULL);
@ -668,7 +682,7 @@ EXPORT_SYMBOL_GPL(of_platform_device_destroy);
* @parent: device which children will be removed
*
* Complementary to of_platform_populate(), this function removes children
* of the given device (and, recurrently, their children) that have been
* of the given device (and, recursively, their children) that have been
* created from their respective device tree nodes (and only those,
* leaving others - eg. manually created - unharmed).
*/
@ -737,7 +751,7 @@ static int devm_of_platform_match(struct device *dev, void *res, void *data)
* @dev: device that requested to depopulate from device tree data
*
* Complementary to devm_of_platform_populate(), this function removes children
* of the given device (and, recurrently, their children) that have been
* of the given device (and, recursively, their children) that have been
* created from their respective device tree nodes (and only those,
* leaving others - eg. manually created - unharmed).
*/

7
drivers/of/property.c
View File

@ -441,6 +441,7 @@ int of_property_read_string(const struct device_node *np, const char *propname,
const char **out_string)
{
const struct property *prop = of_find_property(np, propname, NULL);
if (!prop)
return -EINVAL;
if (!prop->length)
@ -1217,9 +1218,9 @@ static struct device_node *parse_##fname(struct device_node *np, \
*
* @parse_prop: function name
* parse_prop() finds the node corresponding to a supplier phandle
* @parse_prop.np: Pointer to device node holding supplier phandle property
* @parse_prop.prop_name: Name of property holding a phandle value
* @parse_prop.index: For properties holding a list of phandles, this is the
* parse_prop.np: Pointer to device node holding supplier phandle property
* parse_prop.prop_name: Name of property holding a phandle value
* parse_prop.index: For properties holding a list of phandles, this is the
* index into the list
* @optional: Describes whether a supplier is mandatory or not
* @node_not_dev: The consumer node containing the property is never converted

10
drivers/of/unittest-data/tests-phandle.dtsi
View File

@ -40,6 +40,13 @@ provider4: provider4 {
phandle-map-pass-thru = <0x0 0xf0>;
};
provider5: provider5 {
#phandle-cells = <2>;
phandle-map = <2 7 &provider4 2 3>;
phandle-map-mask = <0xff 0xf>;
phandle-map-pass-thru = <0x0 0xf0>;
};
consumer-a {
phandle-list = <&provider1 1>,
<&provider2 2 0>,
@ -66,7 +73,8 @@ consumer-b {
<&provider4 4 0x100>,
<&provider4 0 0x61>,
<&provider0>,
<&provider4 19 0x20>;
<&provider4 19 0x20>,
<&provider5 2 7>;
phandle-list-bad-phandle = <12345678 0 0>;
phandle-list-bad-args = <&provider2 1 0>,
<&provider4 0>;

68
drivers/of/unittest.c
View File

@ -456,6 +456,9 @@ static void __init of_unittest_parse_phandle_with_args(void)
unittest(passed, "index %i - data error on node %pOF rc=%i\n",
i, args.np, rc);
if (rc == 0)
of_node_put(args.np);
}
/* Check for missing list property */
@ -545,8 +548,9 @@ static void __init of_unittest_parse_phandle_with_args(void)
static void __init of_unittest_parse_phandle_with_args_map(void)
{
struct device_node *np, *p0, *p1, *p2, *p3;
struct device_node *np, *p[6] = {};
struct of_phandle_args args;
unsigned int prefs[6];
int i, rc;
np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-b");
@ -555,34 +559,24 @@ static void __init of_unittest_parse_phandle_with_args_map(void)
return;
}
p0 = of_find_node_by_path("/testcase-data/phandle-tests/provider0");
if (!p0) {
p[0] = of_find_node_by_path("/testcase-data/phandle-tests/provider0");
p[1] = of_find_node_by_path("/testcase-data/phandle-tests/provider1");
p[2] = of_find_node_by_path("/testcase-data/phandle-tests/provider2");
p[3] = of_find_node_by_path("/testcase-data/phandle-tests/provider3");
p[4] = of_find_node_by_path("/testcase-data/phandle-tests/provider4");
p[5] = of_find_node_by_path("/testcase-data/phandle-tests/provider5");
for (i = 0; i < ARRAY_SIZE(p); ++i) {
if (!p[i]) {
pr_err("missing testcase data\n");
return;
}
p1 = of_find_node_by_path("/testcase-data/phandle-tests/provider1");
if (!p1) {
pr_err("missing testcase data\n");
return;
}
p2 = of_find_node_by_path("/testcase-data/phandle-tests/provider2");
if (!p2) {
pr_err("missing testcase data\n");
return;
}
p3 = of_find_node_by_path("/testcase-data/phandle-tests/provider3");
if (!p3) {
pr_err("missing testcase data\n");
return;
prefs[i] = kref_read(&p[i]->kobj.kref);
}
rc = of_count_phandle_with_args(np, "phandle-list", "#phandle-cells");
unittest(rc == 7, "of_count_phandle_with_args() returned %i, expected 7\n", rc);
unittest(rc == 8, "of_count_phandle_with_args() returned %i, expected 8\n", rc);
for (i = 0; i < 8; i++) {
for (i = 0; i < 9; i++) {
bool passed = true;
memset(&args, 0, sizeof(args));
@ -593,13 +587,13 @@ static void __init of_unittest_parse_phandle_with_args_map(void)
switch (i) {
case 0:
passed &= !rc;
passed &= (args.np == p1);
passed &= (args.np == p[1]);
passed &= (args.args_count == 1);
passed &= (args.args[0] == 1);
break;
case 1:
passed &= !rc;
passed &= (args.np == p3);
passed &= (args.np == p[3]);
passed &= (args.args_count == 3);
passed &= (args.args[0] == 2);
passed &= (args.args[1] == 5);
@ -610,28 +604,36 @@ static void __init of_unittest_parse_phandle_with_args_map(void)
break;
case 3:
passed &= !rc;
passed &= (args.np == p0);
passed &= (args.np == p[0]);
passed &= (args.args_count == 0);
break;
case 4:
passed &= !rc;
passed &= (args.np == p1);
passed &= (args.np == p[1]);
passed &= (args.args_count == 1);
passed &= (args.args[0] == 3);
break;
case 5:
passed &= !rc;
passed &= (args.np == p0);
passed &= (args.np == p[0]);
passed &= (args.args_count == 0);
break;
case 6:
passed &= !rc;
passed &= (args.np == p2);
passed &= (args.np == p[2]);
passed &= (args.args_count == 2);
passed &= (args.args[0] == 15);
passed &= (args.args[1] == 0x20);
break;
case 7:
passed &= !rc;
passed &= (args.np == p[3]);
passed &= (args.args_count == 3);
passed &= (args.args[0] == 2);
passed &= (args.args[1] == 5);
passed &= (args.args[2] == 3);
break;
case 8:
passed &= (rc == -ENOENT);
break;
default:
@ -640,6 +642,9 @@ static void __init of_unittest_parse_phandle_with_args_map(void)
unittest(passed, "index %i - data error on node %s rc=%i\n",
i, args.np->full_name, rc);
if (rc == 0)
of_node_put(args.np);
}
/* Check for missing list property */
@ -686,6 +691,13 @@ static void __init of_unittest_parse_phandle_with_args_map(void)
"OF: /testcase-data/phandle-tests/consumer-b: #phandle-cells = 2 found 1");
unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc);
for (i = 0; i < ARRAY_SIZE(p); ++i) {
unittest(prefs[i] == kref_read(&p[i]->kobj.kref),
"provider%d: expected:%d got:%d\n",
i, prefs[i], kref_read(&p[i]->kobj.kref));
of_node_put(p[i]);
}
}
static void __init of_unittest_property_string(void)