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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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gpio: 104-idi-48: Implement and utilize register structures
Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. The 104-IDI-48 device features an Intel 8255 compatible GPIO interface, so the i8255 GPIO module is selected and utilized as well. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: John Hentges <jhentges@accesio.com> Cc: Jay Dolan <jay.dolan@accesio.com> Signed-off-by: William Breathitt Gray <william.gray@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
This commit is contained in:
William Breathitt Gray
Bartosz Golaszewski
parent
71b7b39725
commit
3ce632fdd1
@ -865,6 +865,7 @@ config GPIO_104_IDI_48
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depends on PC104
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select ISA_BUS_API
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select GPIOLIB_IRQCHIP
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select GPIO_I8255
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help
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Enables GPIO support for the ACCES 104-IDI-48 family (104-IDI-48A,
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104-IDI-48AC, 104-IDI-48B, 104-IDI-48BC). The base port addresses for
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@ -6,8 +6,7 @@
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* This driver supports the following ACCES devices: 104-IDI-48A,
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* 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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@ -20,6 +19,11 @@
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "gpio-i8255.h"
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MODULE_IMPORT_NS(I8255);
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#define IDI_48_EXTENT 8
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#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
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@ -33,21 +37,34 @@ static unsigned int irq[MAX_NUM_IDI_48];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
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/**
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* struct idi_48_reg - device register structure
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* @port0: Port 0 Inputs
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* @unused: Unused
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* @port1: Port 1 Inputs
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* @irq: Read: IRQ Status Register/IRQ Clear
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* Write: IRQ Enable/Disable
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*/
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struct idi_48_reg {
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u8 port0[3];
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u8 unused;
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u8 port1[3];
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u8 irq;
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};
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/**
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* struct idi_48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @lock: synchronization lock to prevent I/O race conditions
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* @ack_lock: synchronization lock to prevent IRQ handler race conditions
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* @irq_mask: input bits affected by interrupts
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* @base: base port address of the GPIO device
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* @reg: I/O address offset for the device registers
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* @cos_enb: Change-Of-State IRQ enable boundaries mask
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*/
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struct idi_48_gpio {
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struct gpio_chip chip;
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raw_spinlock_t lock;
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spinlock_t ack_lock;
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spinlock_t lock;
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unsigned char irq_mask[6];
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void __iomem *base;
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struct idi_48_reg __iomem *reg;
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unsigned char cos_enb;
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};
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@ -64,42 +81,18 @@ static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned int offs
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static int idi_48_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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unsigned int i;
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static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 };
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void __iomem *port_addr;
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unsigned int mask;
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void __iomem *const ppi = idi48gpio->reg;
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for (i = 0; i < 48; i += 8)
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if (offset < i + 8) {
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port_addr = idi48gpio->base + register_offset[i / 8];
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mask = BIT(offset - i);
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return !!(ioread8(port_addr) & mask);
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}
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/* The following line should never execute since offset < 48 */
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return 0;
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return i8255_get(ppi, offset);
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}
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static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
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unsigned long *bits)
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{
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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unsigned long offset;
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unsigned long gpio_mask;
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static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
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void __iomem *port_addr;
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unsigned long port_state;
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void __iomem *const ppi = idi48gpio->reg;
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/* clear bits array to a clean slate */
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bitmap_zero(bits, chip->ngpio);
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for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
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port_addr = idi48gpio->base + ports[offset / 8];
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port_state = ioread8(port_addr) & gpio_mask;
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bitmap_set_value8(bits, port_state, offset);
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}
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i8255_get_multiple(ppi, mask, bits, chip->ngpio);
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return 0;
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}
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@ -113,30 +106,24 @@ static void idi_48_irq_mask(struct irq_data *data)
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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const unsigned int offset = irqd_to_hwirq(data);
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unsigned int i;
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unsigned int mask;
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unsigned int boundary;
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const unsigned long boundary = offset / 8;
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const unsigned long mask = BIT(offset % 8);
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unsigned long flags;
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for (i = 0; i < 48; i += 8)
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if (offset < i + 8) {
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mask = BIT(offset - i);
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boundary = i / 8;
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spin_lock_irqsave(&idi48gpio->lock, flags);
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idi48gpio->irq_mask[boundary] &= ~mask;
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idi48gpio->irq_mask[boundary] &= ~mask;
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if (!idi48gpio->irq_mask[boundary]) {
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idi48gpio->cos_enb &= ~BIT(boundary);
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/* Exit early if there are still input lines with IRQ unmasked */
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if (idi48gpio->irq_mask[boundary])
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goto exit;
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raw_spin_lock_irqsave(&idi48gpio->lock, flags);
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idi48gpio->cos_enb &= ~BIT(boundary);
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iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7);
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iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
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raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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return;
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}
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exit:
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spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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static void idi_48_irq_unmask(struct irq_data *data)
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@ -144,32 +131,27 @@ static void idi_48_irq_unmask(struct irq_data *data)
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
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const unsigned int offset = irqd_to_hwirq(data);
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unsigned int i;
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unsigned int mask;
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unsigned int boundary;
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const unsigned long boundary = offset / 8;
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const unsigned long mask = BIT(offset % 8);
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unsigned int prev_irq_mask;
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unsigned long flags;
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for (i = 0; i < 48; i += 8)
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if (offset < i + 8) {
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mask = BIT(offset - i);
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boundary = i / 8;
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prev_irq_mask = idi48gpio->irq_mask[boundary];
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spin_lock_irqsave(&idi48gpio->lock, flags);
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idi48gpio->irq_mask[boundary] |= mask;
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prev_irq_mask = idi48gpio->irq_mask[boundary];
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if (!prev_irq_mask) {
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idi48gpio->cos_enb |= BIT(boundary);
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idi48gpio->irq_mask[boundary] |= mask;
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raw_spin_lock_irqsave(&idi48gpio->lock, flags);
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/* Exit early if IRQ was already unmasked for this boundary */
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if (prev_irq_mask)
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goto exit;
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iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7);
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idi48gpio->cos_enb |= BIT(boundary);
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raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
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return;
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}
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exit:
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spin_unlock_irqrestore(&idi48gpio->lock, flags);
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}
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static int idi_48_irq_set_type(struct irq_data *data, unsigned int flow_type)
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@ -200,17 +182,13 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
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unsigned long gpio;
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struct gpio_chip *const chip = &idi48gpio->chip;
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spin_lock(&idi48gpio->ack_lock);
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spin_lock(&idi48gpio->lock);
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raw_spin_lock(&idi48gpio->lock);
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cos_status = ioread8(idi48gpio->base + 7);
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raw_spin_unlock(&idi48gpio->lock);
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cos_status = ioread8(&idi48gpio->reg->irq);
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/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
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if (cos_status & BIT(6)) {
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spin_unlock(&idi48gpio->ack_lock);
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spin_unlock(&idi48gpio->lock);
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return IRQ_NONE;
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}
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@ -228,7 +206,7 @@ static irqreturn_t idi_48_irq_handler(int irq, void *dev_id)
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}
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}
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spin_unlock(&idi48gpio->ack_lock);
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spin_unlock(&idi48gpio->lock);
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return IRQ_HANDLED;
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}
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@ -250,8 +228,8 @@ static int idi_48_irq_init_hw(struct gpio_chip *gc)
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struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
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/* Disable IRQ by default */
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iowrite8(0, idi48gpio->base + 7);
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ioread8(idi48gpio->base + 7);
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iowrite8(0, &idi48gpio->reg->irq);
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ioread8(&idi48gpio->reg->irq);
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return 0;
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}
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@ -273,8 +251,8 @@ static int idi_48_probe(struct device *dev, unsigned int id)
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return -EBUSY;
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}
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idi48gpio->base = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
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if (!idi48gpio->base)
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idi48gpio->reg = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
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if (!idi48gpio->reg)
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return -ENOMEM;
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idi48gpio->chip.label = name;
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@ -298,8 +276,7 @@ static int idi_48_probe(struct device *dev, unsigned int id)
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girq->handler = handle_edge_irq;
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girq->init_hw = idi_48_irq_init_hw;
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raw_spin_lock_init(&idi48gpio->lock);
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spin_lock_init(&idi48gpio->ack_lock);
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spin_lock_init(&idi48gpio->lock);
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err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
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if (err) {
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