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Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next
Pull x86/UV changes from Ingo Molnar: "Continued updates for SGI UV 3 hardware support" * 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/UV: Fix conditional in gru_exit() x86/UV: Set n_lshift based on GAM_GR_CONFIG MMR for UV3
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@ -5,7 +5,7 @@
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*
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* SGI UV architectural definitions
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*
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* Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_HUB_H
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@ -204,16 +204,6 @@ static inline int is_uvx_hub(void)
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return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
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}
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static inline int is_uv2_1_hub(void)
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{
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return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE;
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}
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static inline int is_uv2_2_hub(void)
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{
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return uv_hub_info->hub_revision == UV2_HUB_REVISION_BASE + 1;
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}
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union uvh_apicid {
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unsigned long v;
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struct uvh_apicid_s {
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@ -5,7 +5,7 @@
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*
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* SGI UV MMR definitions
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*
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* Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_X86_UV_UV_MMRS_H
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@ -2802,6 +2802,46 @@ union uv1h_lb_target_physical_apic_id_mask_u {
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} s1;
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};
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/* ========================================================================= */
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/* UV3H_GR0_GAM_GR_CONFIG */
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/* ========================================================================= */
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#define UV3H_GR0_GAM_GR_CONFIG 0xc00028UL
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#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0
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#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10
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#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
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union uv3h_gr0_gam_gr_config_u {
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unsigned long v;
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struct uv3h_gr0_gam_gr_config_s {
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unsigned long m_skt:6; /* RW */
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unsigned long undef_6_9:4; /* Undefined */
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unsigned long subspace:1; /* RW */
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unsigned long reserved:53;
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} s3;
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};
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/* ========================================================================= */
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/* UV3H_GR1_GAM_GR_CONFIG */
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/* ========================================================================= */
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#define UV3H_GR1_GAM_GR_CONFIG 0x1000028UL
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#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT 0
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#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT 10
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#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
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union uv3h_gr1_gam_gr_config_u {
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unsigned long v;
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struct uv3h_gr1_gam_gr_config_s {
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unsigned long m_skt:6; /* RW */
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unsigned long undef_6_9:4; /* Undefined */
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unsigned long subspace:1; /* RW */
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unsigned long reserved:53;
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} s3;
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};
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/* ========================================================================= */
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/* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */
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/* ========================================================================= */
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@ -5,7 +5,7 @@
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*
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* SGI UV APIC functions (note: not an Intel compatible APIC)
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*
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* Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/cpumask.h>
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#include <linux/hardirq.h>
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@ -440,6 +440,20 @@ static __initdata struct redir_addr redir_addrs[] = {
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{UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
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};
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static unsigned char get_n_lshift(int m_val)
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{
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union uv3h_gr0_gam_gr_config_u m_gr_config;
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if (is_uv1_hub())
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return m_val;
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if (is_uv2_hub())
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return m_val == 40 ? 40 : 39;
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m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
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return m_gr_config.s3.m_skt;
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}
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static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
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{
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union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
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@ -849,6 +863,7 @@ void __init uv_system_init(void)
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int gnode_extra, min_pnode = 999999, max_pnode = -1;
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unsigned long mmr_base, present, paddr;
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unsigned short pnode_mask;
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unsigned char n_lshift;
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char *hub = (is_uv1_hub() ? "UV1" :
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(is_uv2_hub() ? "UV2" :
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"UV3"));
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@ -860,6 +875,7 @@ void __init uv_system_init(void)
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m_val = m_n_config.s.m_skt;
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n_val = m_n_config.s.n_skt;
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pnode_mask = (1 << n_val) - 1;
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n_lshift = get_n_lshift(m_val);
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mmr_base =
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uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
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~UV_MMR_ENABLE;
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@ -867,8 +883,9 @@ void __init uv_system_init(void)
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node_id.v = uv_read_local_mmr(UVH_NODE_ID);
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gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
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gnode_upper = ((unsigned long)gnode_extra << m_val);
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pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x\n",
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n_val, m_val, pnode_mask, gnode_upper, gnode_extra);
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pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n",
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n_val, m_val, pnode_mask, gnode_upper, gnode_extra,
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n_lshift);
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pr_info("UV: global MMR base 0x%lx\n", mmr_base);
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@ -935,8 +952,7 @@ void __init uv_system_init(void)
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uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
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uv_cpu_hub_info(cpu)->m_shift = 64 - m_val;
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uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ?
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(m_val == 40 ? 40 : 39) : m_val;
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uv_cpu_hub_info(cpu)->n_lshift = n_lshift;
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pnode = uv_apicid_to_pnode(apicid);
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blade = boot_pnode_to_blade(pnode);
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* This file supports the user system call for file open, close, mmap, etc.
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* This also incudes the driver initialization code.
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*
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* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (c) 2008-2014 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -58,6 +58,11 @@ static int max_user_cbrs, max_user_dsr_bytes;
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static struct miscdevice gru_miscdev;
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static int gru_supported(void)
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{
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return is_uv_system() &&
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(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE);
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}
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/*
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* gru_vma_close
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@ -518,7 +523,7 @@ static int __init gru_init(void)
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{
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int ret;
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if (!is_uv_system() || (is_uvx_hub() && !is_uv2_hub()))
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if (!gru_supported())
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return 0;
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#if defined CONFIG_IA64
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@ -573,7 +578,7 @@ static int __init gru_init(void)
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static void __exit gru_exit(void)
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{
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if (!is_uv_system())
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if (!gru_supported())
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return;
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gru_teardown_tlb_irqs();
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