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drm/i915/cnl: Add Cannonlake PCI IDs for another SKU.
The only difference is that this SKUs has the full
Port A/E split named as Port F.
But since SKUs differences don't matter on the platform
definition group and ids, let's merge all off them together.
v2: Really include the PCI IDs to the picidlist[];
v3: Add the PCI Id for another SKU (Anusha).
v4: Update IDs, really include to pciidlists again.
v5: Unify all GT2 IDs.
v6: Unify in a way that we don't break early-quirks.c
v7: Remove GT reference since it doesn't matter here (Paulo)
Also move IS_CNL_WITH_PORT_F macro to this patch to
make it easier for review this part and also to get
used sooner.
v8: Rebased on top of commit 5db47e37b3
("Revert "drm/i915:
mark all device info struct with __initconst"")
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-1-rodrigo.vivi@intel.com
This commit is contained in:
parent
394676f05b
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@ -2648,6 +2648,8 @@ intel_info(const struct drm_i915_private *dev_priv)
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(dev_priv)->info.gt == 2)
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#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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(dev_priv)->info.gt == 3)
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#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
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#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
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@ -571,7 +571,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
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.ddb_size = 1024, \
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GLK_COLORS
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static const struct intel_device_info intel_cannonlake_gt2_info = {
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static const struct intel_device_info intel_cannonlake_info = {
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GEN10_FEATURES,
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.is_alpha_support = 1,
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.platform = INTEL_CANNONLAKE,
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@ -649,8 +649,7 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
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INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
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INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
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INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
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INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
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INTEL_CNL_IDS(&intel_cannonlake_info),
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{0, 0, 0}
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};
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MODULE_DEVICE_TABLE(pci, pciidlist);
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@ -414,24 +414,20 @@
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INTEL_CFL_U_GT2_IDS(info), \
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INTEL_CFL_U_GT3_IDS(info)
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/* CNL U 2+2 */
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#define INTEL_CNL_U_GT2_IDS(info) \
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/* CNL */
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#define INTEL_CNL_IDS(info) \
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INTEL_VGA_DEVICE(0x5A52, info), \
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INTEL_VGA_DEVICE(0x5A5A, info), \
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INTEL_VGA_DEVICE(0x5A42, info), \
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INTEL_VGA_DEVICE(0x5A4A, info)
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/* CNL Y 2+2 */
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#define INTEL_CNL_Y_GT2_IDS(info) \
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INTEL_VGA_DEVICE(0x5A4A, info), \
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INTEL_VGA_DEVICE(0x5A51, info), \
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INTEL_VGA_DEVICE(0x5A59, info), \
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INTEL_VGA_DEVICE(0x5A41, info), \
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INTEL_VGA_DEVICE(0x5A49, info), \
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INTEL_VGA_DEVICE(0x5A71, info), \
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INTEL_VGA_DEVICE(0x5A79, info)
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#define INTEL_CNL_IDS(info) \
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INTEL_CNL_U_GT2_IDS(info), \
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INTEL_CNL_Y_GT2_IDS(info)
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INTEL_VGA_DEVICE(0x5A79, info), \
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INTEL_VGA_DEVICE(0x5A54, info), \
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INTEL_VGA_DEVICE(0x5A5C, info), \
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INTEL_VGA_DEVICE(0x5A44, info)
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#endif /* _I915_PCIIDS_H */
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