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OMAP2+: powerdomain: fix bank power state bitfields

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The bank power state bitfields in the powerdomain data are
encoded incorrectly.  These fields are intended to be bitfields,
representing a set of power states that the memory banks support.
However, when only one power state was supported by a given bank,
the field was incorrectly set to the bit shift -- not the mask.
While here, update some file copyrights.

The OMAP4 autogeneration scripts have been updated accordingly.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Paul Walmsley 2011-03-07 19:28:15 -07:00
parent cad7a34b3a
commit 4cb49fec12
4 changed files with 73 additions and 73 deletions
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6
arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
View File

@ -62,13 +62,13 @@ struct powerdomain gfx_omap2_pwrdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
CHIP_IS_OMAP3430ES1), CHIP_IS_OMAP3430ES1),
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };

18
arch/arm/mach-omap2/powerdomains2xxx_data.c
View File

@ -2,7 +2,7 @@
* OMAP2XXX powerdomain definitions * OMAP2XXX powerdomain definitions
* *
* Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation * Copyright (C) 2007-2011 Nokia Corporation
* *
* Paul Walmsley, Jouni Högander * Paul Walmsley, Jouni Högander
* *
@ -30,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
.prcm_offs = OMAP24XX_DSP_MOD, .prcm_offs = OMAP24XX_DSP_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, [0] = PWRSTS_RET,
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, [0] = PWRSTS_ON,
}, },
}; };
@ -48,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, [0] = PWRSTS_RET,
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, [0] = PWRSTS_ON,
}, },
}; };
@ -87,13 +87,13 @@ static struct powerdomain mdm_pwrdm = {
.prcm_offs = OMAP2430_MDM_MOD, .prcm_offs = OMAP2430_MDM_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };

38
arch/arm/mach-omap2/powerdomains3xxx_data.c
View File

@ -2,7 +2,7 @@
* OMAP3 powerdomain definitions * OMAP3 powerdomain definitions
* *
* Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2010 Nokia Corporation * Copyright (C) 2007-2011 Nokia Corporation
* *
* Paul Walmsley, Jouni Högander * Paul Walmsley, Jouni Högander
* *
@ -47,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
[3] = PWRSTS_OFF_RET, [3] = PWRSTS_OFF_RET,
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, [0] = PWRSTS_ON,
[1] = PWRDM_POWER_ON, [1] = PWRSTS_ON,
[2] = PWRSTS_OFF_ON, [2] = PWRSTS_OFF_ON,
[3] = PWRDM_POWER_ON, [3] = PWRSTS_ON,
}, },
}; };
@ -128,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_DSS_MOD, .prcm_offs = OMAP3430_DSS_MOD,
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };
@ -149,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
/* XXX This is accurate for 3430 SGX, but what about GFX? */ /* XXX This is accurate for 3430 SGX, but what about GFX? */
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };
@ -164,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.prcm_offs = OMAP3430_CAM_MOD, .prcm_offs = OMAP3430_CAM_MOD,
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };
@ -182,10 +182,10 @@ static struct powerdomain per_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };
@ -200,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
.prcm_offs = OMAP3430_NEON_MOD, .prcm_offs = OMAP3430_NEON_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
}; };
static struct powerdomain usbhost_pwrdm = { static struct powerdomain usbhost_pwrdm = {
@ -208,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
.prcm_offs = OMAP3430ES2_USBHOST_MOD, .prcm_offs = OMAP3430ES2_USBHOST_MOD,
.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
.pwrsts = PWRSTS_OFF_RET_ON, .pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_RET, .pwrsts_logic_ret = PWRSTS_RET,
/* /*
* REVISIT: Enabling usb host save and restore mechanism seems to * REVISIT: Enabling usb host save and restore mechanism seems to
* leave the usb host domain permanently in ACTIVE mode after * leave the usb host domain permanently in ACTIVE mode after
@ -218,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
/*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* MEMRETSTATE */ [0] = PWRSTS_RET, /* MEMRETSTATE */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* MEMONSTATE */ [0] = PWRSTS_ON, /* MEMONSTATE */
}, },
}; };

84
arch/arm/mach-omap2/powerdomains44xx_data.c
View File

@ -2,7 +2,7 @@
* OMAP4 Power domains framework * OMAP4 Power domains framework
* *
* Copyright (C) 2009-2010 Texas Instruments, Inc. * Copyright (C) 2009-2010 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation * Copyright (C) 2009-2011 Nokia Corporation
* *
* Abhijit Pagare (abhijitpagare@ti.com) * Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com) * Benoit Cousson (b-cousson@ti.com)
@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 5, .banks = 5,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* core_nret_bank */ [0] = PWRSTS_OFF, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */ [1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRDM_POWER_RET, /* core_other_bank */ [2] = PWRSTS_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ducati_l2ram */ [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
[4] = PWRSTS_OFF_RET, /* ducati_unicache */ [4] = PWRSTS_OFF_RET, /* ducati_unicache */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* core_nret_bank */ [0] = PWRSTS_ON, /* core_nret_bank */
[1] = PWRSTS_OFF_RET, /* core_ocmram */ [1] = PWRSTS_OFF_RET, /* core_ocmram */
[2] = PWRDM_POWER_ON, /* core_other_bank */ [2] = PWRSTS_ON, /* core_other_bank */
[3] = PWRDM_POWER_ON, /* ducati_l2ram */ [3] = PWRSTS_ON, /* ducati_l2ram */
[4] = PWRDM_POWER_ON, /* ducati_unicache */ [4] = PWRSTS_ON, /* ducati_unicache */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* gfx_mem */ [0] = PWRSTS_OFF, /* gfx_mem */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* gfx_mem */ [0] = PWRSTS_ON, /* gfx_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -83,12 +83,12 @@ static struct powerdomain abe_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF, .pwrsts_logic_ret = PWRSTS_OFF,
.banks = 2, .banks = 2,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* aessmem */ [0] = PWRSTS_RET, /* aessmem */
[1] = PWRDM_POWER_OFF, /* periphmem */ [1] = PWRSTS_OFF, /* periphmem */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* aessmem */ [0] = PWRSTS_ON, /* aessmem */
[1] = PWRDM_POWER_ON, /* periphmem */ [1] = PWRSTS_ON, /* periphmem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF, .pwrsts_logic_ret = PWRSTS_OFF,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* dss_mem */ [0] = PWRSTS_OFF, /* dss_mem */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* dss_mem */ [0] = PWRSTS_ON, /* dss_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3, .banks = 3,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_RET, /* tesla_edma */ [0] = PWRSTS_RET, /* tesla_edma */
[1] = PWRSTS_OFF_RET, /* tesla_l1 */ [1] = PWRSTS_OFF_RET, /* tesla_l1 */
[2] = PWRSTS_OFF_RET, /* tesla_l2 */ [2] = PWRSTS_OFF_RET, /* tesla_l2 */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* tesla_edma */ [0] = PWRSTS_ON, /* tesla_edma */
[1] = PWRDM_POWER_ON, /* tesla_l1 */ [1] = PWRSTS_ON, /* tesla_l1 */
[2] = PWRDM_POWER_ON, /* tesla_l2 */ [2] = PWRSTS_ON, /* tesla_l2 */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
.pwrsts = PWRSTS_ON, .pwrsts = PWRSTS_ON,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* wkup_bank */ [0] = PWRSTS_OFF, /* wkup_bank */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* wkup_bank */ [0] = PWRSTS_ON, /* wkup_bank */
}, },
}; };
@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
[0] = PWRSTS_OFF_RET, /* cpu0_l1 */ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* cpu0_l1 */ [0] = PWRSTS_ON, /* cpu0_l1 */
}, },
}; };
@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
[0] = PWRSTS_OFF_RET, /* cpu1_l1 */ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* cpu1_l1 */ [0] = PWRSTS_ON, /* cpu1_l1 */
}, },
}; };
@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* emu_bank */ [0] = PWRSTS_OFF, /* emu_bank */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* emu_bank */ [0] = PWRSTS_ON, /* emu_bank */
}, },
}; };
@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRSTS_OFF_RET, /* mpu_l1 */ [0] = PWRSTS_OFF_RET, /* mpu_l1 */
[1] = PWRSTS_OFF_RET, /* mpu_l2 */ [1] = PWRSTS_OFF_RET, /* mpu_l2 */
[2] = PWRDM_POWER_RET, /* mpu_ram */ [2] = PWRSTS_RET, /* mpu_ram */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* mpu_l1 */ [0] = PWRSTS_ON, /* mpu_l1 */
[1] = PWRDM_POWER_ON, /* mpu_l2 */ [1] = PWRSTS_ON, /* mpu_l2 */
[2] = PWRDM_POWER_ON, /* mpu_ram */ [2] = PWRSTS_ON, /* mpu_ram */
}, },
}; };
@ -230,16 +230,16 @@ static struct powerdomain ivahd_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF, .pwrsts_logic_ret = PWRSTS_OFF,
.banks = 4, .banks = 4,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* hwa_mem */ [0] = PWRSTS_OFF, /* hwa_mem */
[1] = PWRSTS_OFF_RET, /* sl2_mem */ [1] = PWRSTS_OFF_RET, /* sl2_mem */
[2] = PWRSTS_OFF_RET, /* tcm1_mem */ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
[3] = PWRSTS_OFF_RET, /* tcm2_mem */ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* hwa_mem */ [0] = PWRSTS_ON, /* hwa_mem */
[1] = PWRDM_POWER_ON, /* sl2_mem */ [1] = PWRSTS_ON, /* sl2_mem */
[2] = PWRDM_POWER_ON, /* tcm1_mem */ [2] = PWRSTS_ON, /* tcm1_mem */
[3] = PWRDM_POWER_ON, /* tcm2_mem */ [3] = PWRSTS_ON, /* tcm2_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* cam_mem */ [0] = PWRSTS_OFF, /* cam_mem */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* cam_mem */ [0] = PWRSTS_ON, /* cam_mem */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 1, .banks = 1,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* l3init_bank1 */ [0] = PWRSTS_OFF, /* l3init_bank1 */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* l3init_bank1 */ [0] = PWRSTS_ON, /* l3init_bank1 */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };
@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
.pwrsts_logic_ret = PWRSTS_OFF_RET, .pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 2, .banks = 2,
.pwrsts_mem_ret = { .pwrsts_mem_ret = {
[0] = PWRDM_POWER_OFF, /* nonretained_bank */ [0] = PWRSTS_OFF, /* nonretained_bank */
[1] = PWRDM_POWER_RET, /* retained_bank */ [1] = PWRSTS_RET, /* retained_bank */
}, },
.pwrsts_mem_on = { .pwrsts_mem_on = {
[0] = PWRDM_POWER_ON, /* nonretained_bank */ [0] = PWRSTS_ON, /* nonretained_bank */
[1] = PWRDM_POWER_ON, /* retained_bank */ [1] = PWRSTS_ON, /* retained_bank */
}, },
.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
}; };